PIC16C72-10/SP Microchip Technology, PIC16C72-10/SP Datasheet - Page 42

• Manufacturer Part Number: PIC16C72-10/SP
• Description: IC MCU OTP 2KX14 A/D PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-10/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC16C72-10/SPR; PIC16C72-10/SPR

PIC16C72 Series
8.2.1
A block diagram of the SSP Module in SPI Mode is
shown in Figure 8-3.
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:
• Master Operation (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Output/Input data on the Rising/
• Clock Rate (master operation only)
• Slave Select Mode (Slave mode only)
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear enable bit SSPEN, re-initialize SSPCON
register, and then set enable bit SSPEN. This config-
ures the SDI, SDO, SCK, and SS pins as serial port
pins. For the pins to behave as the serial port function,
they must have their data direction bits (in the TRIS reg-
ister) appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (master operation) must have TRISC<3>
TABLE 8-1
DS39016A-page 42
Address
0Bh,8Bh
0Ch
8Ch
87h
13h
14h
85h
94h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1:
Falling edge of SCK)
cleared
OPERATION OF SSP MODULE IN SPI
MODE - PIC16C72
These bits are unimplemented, read as '0'.
Name
INTCON
PIR1
PIE1
TRISC
SSPBUF
SSPCON
TRISA
SSP-
STAT
REGISTERS ASSOCIATED WITH SPI OPERATION
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
Bit 7
GIE
(1)
(1)
—
—
RC4/SDI/SDA
RC3/SCK/SCL
RA5/SS/AN4
SSPOV SSPEN
PEIE
ADIF
ADIE
Bit 6
—
—
PORTA Data Direction Register
Bit 5
T0IE
D/A
(1)
(1)
Preliminary
INTE
Bit 4
CKP
(1)
(1)
P
SSPM3 SSPM2 SSPM1
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIF
RBIE
Bit 3
S
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set (if implemented)
FIGURE 8-3:
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SCL
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
Bit 2
T0IF
R/W
INTF
Bit 1
UA
Read
SS Control
SSP BLOCK DIAGRAM
(SPI MODE)
Select
TRISC<3>
Edge
SSPM3:SSPM0
Enable
bit0
Select
Edge
SSPM0 0000 0000 0000 0000
SSPBUF reg
RBIF
Bit 0
BF
SSPSR reg
1998 Microchip Technology Inc.
Clock Select
4
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
--00 0000 --00 0000
Value on:
2
POR,
BOR
Write
Prescaler
4, 16, 64
clock
shift
TMR2 output
data bus
Internal
Value on
all other
resets
2
T
CY