PIC16C72-10/SP Microchip Technology, PIC16C72-10/SP Datasheet - Page 8

• Manufacturer Part Number: PIC16C72-10/SP
• Description: IC MCU OTP 2KX14 A/D PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-10/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC16C72-10/SPR; PIC16C72-10/SPR

PIC16C72 Series
TABLE 2-1
DS39016A-page 8
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: These registers can be addressed from either bank.
Address Name
Bank 1
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
PIE1
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PCON
PR2
SSPADD
SSPSTAT
ADCON1
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
SMP
RBPU
IRP
Bit 7
GIE
—
—
—
—
—
(4)
(5)
INTEDG
CKE
RP1
ADIE
Bit 6
PEIE
—
—
—
—
(4)
(5)
PORTA Data Direction Register
2
C mode) Address Register
T0CS
Bit 5
T0IE
RP0
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the PC
Preliminary
T0SE
Bit 4
INTE
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
S
CCP1IE
PCFG2
Bit 2
T0IF
R/W
PS2
—
Z
TMR2IE
PCFG1
INTF
Bit 1
POR
PS1
DC
UA
1998 Microchip Technology Inc.
TMR1IE
PCFG0
Bit 0
RBIF
BOR
PS0
BF
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
---- -000
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—