DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

dsPIC30F3014/4013
15. 8x PLL Mode
16. Low-Voltage Detect (LVD)
17. I/O Port – Port Pin Multiplexed with IC1
18. Timer Module
19. PLL Lock Status Bit
20. PSV Operations
DS80397A-page 2
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
The external Low-Voltage Detect (LVD) module is
not connected to the AN2 Pad.
The Port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
21. I
22. I
23. I
24. I
25. I
The following sections describe the errata and work
around to these errata, where they may apply.
The I
operating as an I
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
2
2
C Module
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
C module loses incoming data bytes when
2
2
C module is enabled, the dsPIC
2
C module is configured as a 10-bit
2
C module is configured for 10-bit
C devices, the A10 and A9 bits may
2
C slave.
© 2008 Microchip Technology Inc.
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