ATMEGA3290P-20AU Atmel, ATMEGA3290P-20AU Datasheet - Page 161
![IC MCU 32K 4X40 LCD CTRL 100TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AU
Manufacturer Part Number
ATMEGA3290P-20AU
Description
IC MCU 32K 4X40 LCD CTRL 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA3290P-16AU
ATMEGA3290P-16AU
ATMEGA3290P-16AU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 161 of 427
- Download datasheet (9Mb)
8021G–AVR–03/11
The interconnection between Master and Slave CPUs with SPI is shown in
161. The system consists of two shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
Master and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted
from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the
Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave
by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 18-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the minimum low and high period should be:
Low period: longer than 2 CPU clock cycles.
High period: longer than 2 CPU clock cycles.
ATmega329P/3290P
SHIFT
ENABLE
Figure 18-2 on page
161
Related parts for ATMEGA3290P-20AU
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![ATmega3290](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
![ATMEGA3290-16AU](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
IC AVR MCU 32K 16MHZ 100TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA3290-16AI](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
IC AVR MCU 32K 16MHZ 100TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA3290-16AUR](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
MCU AVR 32K FLASH 16MHZ 64TQFP
Manufacturer:
Atmel
Datasheet:
![atmega3290v](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Atmega3290 Avr 8-bit Microcontroller With In-system Programmable Flash
Manufacturer:
ATMEL Corporation
Datasheet:
![ATmega329](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
![ATMEGA329-16AU](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
IC AVR MCU 32K 16MHZ 64TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA329-16MU](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
IC AVR MCU 32K 16MHZ 64-QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA329-16AI](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
IC AVR MCU 32K 16MHZ 64TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA329-16MI](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
IC AVR MCU 32K 16MHZ 64-QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA329-16AUR](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
MCU AVR 32K FLASH 16MHZ 64TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA329-16MUR](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
MCU AVR 32K FLASH 16MHZ 64QFN
Manufacturer:
Atmel
Datasheet:
![ATSTK600](/photos/9/20/92038/atstk600_tmb.jpg)
Part Number:
Description:
DEV KIT FOR AVR/AVR32
Manufacturer:
Atmel
Datasheet:
![U641B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet: