ATMEGA3290P-20AU Atmel, ATMEGA3290P-20AU Datasheet - Page 90
![IC MCU 32K 4X40 LCD CTRL 100TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AU
Manufacturer Part Number
ATMEGA3290P-20AU
Description
IC MCU 32K 4X40 LCD CTRL 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA3290P-16AU
ATMEGA3290P-16AU
ATMEGA3290P-16AU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
8021G–AVR–03/11
Register Description
MCUCR – MCU Control Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins Address
PORTB – Port B Data Register
DDRB – Port B Data Direction Register
PINB – Port B Input Pins Address
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 64
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x02 (0x22)
Read/Write
Initial Value
Bit
0x01 (0x21)
Read/Write
Initial Value
Bit
0x00 (0x20)
Read/Write
Initial Value
Bit
0x05 (0x25)
Read/Write
Initial Value
Bit
0x04 (0x24)
Read/Write
Initial Value
Bit
0x03 (0x23)
Read/Write
Initial Value
PORTA7
PORTB7
PINA7
PINB7
DDA7
DDB7
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
R/W
JTD
7
0
7
7
0
7
0
7
0
7
7
0
PORTA6
PORTB6
PINA6
PINB6
DDA6
DDB6
R/W
R/W
R/W
BODS
R/W
R/W
R/W
N/A
N/A
R/W
6
0
6
6
0
6
0
6
0
6
6
0
for more details about this feature.
PORTB5
PORTA5
PINA5
PINB5
DDA5
DDB5
R/W
R/W
R/W
BODSE
R/W
N/A
R/W
R/W
N/A
5
5
0
5
0
5
0
5
0
5
R/W
5
0
PORTB4
PORTA4
PINA4
PINB4
DDA4
DDB4
R/W
R/W
R/W
R/W
N/A
R/W
R/W
N/A
4
4
0
4
0
4
0
4
0
4
PUD
R/W
4
0
PORTB3
PORTA3
PINA3
PINB3
DDA3
DDB3
R/W
R/W
R/W
R/W
N/A
R/W
R/W
N/A
3
3
0
3
0
3
0
3
0
3
R
3
–
0
ATmega329P/3290P
PORTB2
PORTA2
PINA2
PINB2
DDA2
DDB2
R/W
R/W
R/W
N/A
R/W
R/W
R/W
N/A
2
2
0
2
0
2
0
2
0
2
R
2
–
0
PORTB1
PORTA1
PINA1
DDA1
PINB1
DDB1
R/W
R/W
N/A
R/W
R/W
R/W
R/W
IVSEL
N/A
1
R/W
1
0
1
0
1
0
1
0
1
1
0
PORTB0
PORTA0
PINA0
DDA0
PINB0
DDB0
R/W
IVCE
R/W
N/A
R/W
R/W
R/W
R/W
R/W
N/A
0
0
0
0
0
0
0
0
0
0
0
0
MCUCR
PORTA
PORTB
DDRA
DDRB
PINA
PINB
”Con-
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