ATMEGA3290P-20AU Atmel, ATMEGA3290P-20AU Datasheet - Page 265
ATMEGA3290P-20AU
Manufacturer Part Number
ATMEGA3290P-20AU
Description
IC MCU 32K 4X40 LCD CTRL 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA3290P-16AU
ATMEGA3290P-16AU
ATMEGA3290P-16AU
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Table 25-5.
8021G–AVR–03/11
Step
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PR
ELOAD
EXTEST
Verify the
COMP bit
scanned out to
be 0
Verify the
COMP bit
scanned out to
be 1
Algorithm for Using the ADC
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
ADCEN
(Sample mode).
1
1
1
1
1
1
1
1
1
1
1
Table
The lower limit is:
The upper limit is:
DAC
25-5. Only the DAC and port pin values of the Scan Chain are shown. The column
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
Table 25-4
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⋅
⋅
are used unless other values are given in the algo-
⁄
⁄
PRECH
=
=
1
1
1
1
0
1
1
1
1
0
1
291
323
ATmega329P/3290P
=
=
0x123
0x143
PA3.
Data
CC
0
0
0
0
0
0
0
0
0
0
0
.
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Pull-up_
Enable
0
0
0
0
0
0
0
0
0
0
0
265
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