DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 222

• Manufacturer Part Number: DSPIC30F4011-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401120EPT

dsPIC30F4011/4012
Program and EEPROM Characteristics ............................ 176
Program Counter................................................................. 16
Program Data Table Access ............................................... 26
Program Space Visibility
Programmable................................................................... 139
Programmable Digital Noise Filters..................................... 87
Programmer’s Model........................................................... 16
Programming Operations .................................................... 49
Protection Against Accidental Writes to OSCCON ........... 144
PWM Duty Cycle Comparison Units ................................... 95
PWM Fault Pins .................................................................. 98
PWM Operation During CPU Idle Mode.............................. 99
PWM Operation During CPU Sleep Mode .......................... 99
PWM Output and Polarity Control ....................................... 98
PWM Output Override......................................................... 97
PWM Period ........................................................................ 94
PWM Special Event Trigger ................................................ 99
PWM Time Base ................................................................. 93
PWM Update Lockout ......................................................... 99
Q
QEA/QEB Input Characteristics ........................................ 191
QEI Module
Quadrature Decoder Timing Requirements ...................... 191
Quadrature Encoder Interface (QEI) Module ...................... 85
Quadrature Encoder Interface Interrupts ............................ 88
Quadrature Encoder Interface Logic ................................... 86
DS70135C-page 220
Table Instructions
Window into Program Space Operation...................... 27
Diagram ...................................................................... 17
Algorithm for Program Flash ....................................... 49
Erasing a Row of Program Memory ............................ 49
Initiating the Programming Sequence ......................... 50
Loading Write Latches ................................................ 50
Duty Cycle Register Buffers ........................................ 95
Enable Bits.................................................................. 98
Fault States ................................................................. 98
Modes ......................................................................... 98
Output Pin Control ...................................................... 98
Complementary Output Mode ..................................... 97
Synchronization .......................................................... 97
Postscaler ................................................................... 99
Continuous Up/Down Counting Modes ....................... 93
Double Update Mode .................................................. 94
Free Running Mode .................................................... 93
Postscaler ................................................................... 94
Prescaler ..................................................................... 94
Single Shot Mode........................................................ 93
External Clock Timing Requirements........................ 187
Index Pulse Timing Characteristics........................... 192
Index Pulse Timing Requirements ............................ 192
Operation During CPU Idle Mode ............................... 88
Operation During CPU Sleep Mode ............................ 87
Register Map............................................................... 89
Timer Operation During CPU Idle Mode ..................... 88
Timer Operation During CPU Sleep Mode.................. 87
TBLRDH.............................................................. 25
TBLRDL .............................................................. 25
TBLWTH ............................................................. 25
TBLWTL.............................................................. 25
Cycle-by-Cycle.................................................... 98
Latched ............................................................... 98
Preliminary
R
Reset ........................................................................ 139, 145
Reset Sequence ................................................................. 43
Reset Timing Characteristics............................................ 183
Reset Timing Requirements ............................................. 184
Resets
S
Simple Capture Event Mode
Simple OC/PWM Mode Timing Requirements ................. 189
Simple Output Compare Match Mode ................................ 82
Simple PWM Mode ............................................................. 82
Single Pulse PWM Operation ............................................. 97
Software Simulator (MPLAB SIM) .................................... 162
Software Simulator (MPLAB SIM30) ................................ 162
Software Stack Pointer, Frame Pointer .............................. 16
SPI Mode
SPI Module ....................................................................... 101
SPI Operation During CPU Idle Mode .............................. 103
SPI Operation During CPU Sleep Mode........................... 103
Status Register ................................................................... 16
Symbols Used in Opcode Descriptions ............................ 154
System Integration............................................................ 139
T
Temperature and Voltage Specifications
Timer1 Module.................................................................... 63
Reset Sources ............................................................ 43
BOR, Programmable ................................................ 147
POR .......................................................................... 145
POR with Long Crystal Start-up Time....................... 147
POR, Operating without FSCM and PWRT .............. 147
Capture Buffer Operation............................................ 78
Capture Prescaler....................................................... 78
Hall Sensor Mode ....................................................... 78
Input Capture in CPU Idle Mode................................. 79
Timer2 and Timer3 Selection Mode............................ 78
Input Pin Fault Protection ........................................... 82
Period ......................................................................... 83
CALL Stack Frame ..................................................... 31
Slave Select Synchronization ................................... 103
SPI1 Register Map.................................................... 104
Framed SPI Support ................................................. 101
Operating Function Description ................................ 101
SDOx Disable ........................................................... 101
Timing Characteristics
Timing Requirements
Word and Byte Communication ................................ 101
Overview................................................................... 139
Register Map ............................................................ 152
AC............................................................................. 177
DC ............................................................................ 167
16-bit Asynchronous Counter Mode ........................... 63
16-bit Synchronous Counter Mode ............................. 63
16-bit Timer Mode....................................................... 63
Master Mode (CKE = 0).................................... 193
Master Mode (CKE = 1).................................... 194
Slave Mode (CKE = 1).............................. 195, 196
Master Mode (CKE = 0).................................... 193
Master Mode (CKE = 1).................................... 194
Slave Mode (CKE = 0)...................................... 195
Slave Mode (CKE = 1)...................................... 197
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