DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 68

IC DSPIC MCU/DSP 48K 44TQFP

DSPIC30F4011-20E/PT

Manufacturer Part Number
DSPIC30F4011-20E/PT
Description
IC DSPIC MCU/DSP 48K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
9-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F401120EPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
FIGURE 9-1:
9.1
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal T
increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit, TGATE
(T1CON<6>), must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
The input clock (F
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• A write to the TMR1 register
• Clearing of the TON bit (T1CON<15>)
• A device Reset, such as a POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
The TMR1 register is not cleared when the T1CON
register is written. It is cleared by writing to the TMR1
register.
DS70135G-page 68
Timer Gate Operation
Timer Prescaler
SOSCO/
SOSCI
T1IF
Event Flag
T1CK
OSC
/4 or external clock) to the 16-bit
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
TGATE
0
1
Reset
Equal
LPOSCEN
Comparator x 16
TMR1
PR1
CY
to
Q
Q
Gate
Sync
CK
T
D
CY
9.3
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
• The TSYNC bit (T1CON<2>) is asserted to a logic
When all three conditions are true, the timer will
continue to count up to the Period register and be reset
to 0x0000.
When a match between the timer and the Period regis-
ter occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
TGATE
(TCS = 1) and
‘0’, which defines the external clock source as
asynchronous
Timer Operation During Sleep
Mode
1 x
0 1
0 0
TON
TSYNC
1
0
© 2010 Microchip Technology Inc.
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2

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