PIC18F67K22-I/MRRSL Microchip Technology, PIC18F67K22-I/MRRSL Datasheet - Page 504

• Manufacturer Part Number: PIC18F67K22-I/MRRSL
• Description: MCU PIC 128K FLASH XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM180021, DM183026-2, DM183032, DV164131, MA180028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
FIGURE 31-6:
TABLE 31-7:
DS39960B-page 504
150
151
153
154
155
161
162
162A
163
166
167
168
170
170A
Param
AD<7:0>
No
A<19:8>
OSC1
BA0
ALE
Note: Fmax = 25 MHz in 8-Bit External Memory mode.
OE
CE
TadV2aIL
TaIL2adl
B
B
TaIL2oeL
ToeH2adD OE  to A/D Driven
TadV2oeH Least Significant Data Valid Before OE 
TadV2oeH Most Significant Data Valid Before OE 
ToeH2adI
TaIH2aIH
T
Toe
TubH2oeH BA0 = 0 Valid Before OE 
TubL2oeH BA0 = 1 Valid Before OE 
ACC
Symbol
A
A
01
02
PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT)
Address Out Valid to ALE  (address setup time)
ALE  to Address Out Invalid (address hold time)
BA0  to Most Significant Data Valid
BA0  to Least Significant Data Valid
ALE  to OE 
(data setup time
(data setup time)
OE  to Data in Invalid (data Hold Time)
ALE  to ALE  (cycle time)
Address Valid to Data Valid
OE  to Data Valid
Q1
PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT)
Address
Address
150
151
Characteristics
Q2
155
167
Preliminary
168
153
Q3
166
170A
Data
162A
154
Q4
170
0.25 T
0.125 T
0.25 T
0.5 T
163
0.125 T
0.125 T
0.125 T
0.25 T
0.5 T
162
Data
Min
20
CY
—
—
CY
CY
5
0
CY
CY
– 10
CY
– 10
CY
CY
CY
+ 20
– 5
161
 2010 Microchip Technology Inc.
Q1
Typ
T
—
—
—
—
—
—
—
—
—
—
—
—
—
CY
0.125 T
Address
Address
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
CY
Q2
+ 5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns