PIC18F67K22-I/MRRSL Microchip Technology, PIC18F67K22-I/MRRSL Datasheet - Page 519

• Manufacturer Part Number: PIC18F67K22-I/MRRSL
• Description: MCU PIC 128K FLASH XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM180021, DM183026-2, DM183032, DV164131, MA180028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 31-23:
TABLE 31-24: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 31-24:
TABLE 31-25: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
 2010 Microchip Technology Inc.
120
121
122
Param.
125
126
Param
No.
No.
Note:
RXx/DTx
TXx/CKx
Note:
T
T
T
RXx/DTx
TXx/CKx
T
T
CK
CKRF
Symbol
DTRF
CK
Symbol
DT
pin
pin
H2
L2
V2
Refer to Figure 31-3 for load conditions.
pin
pin
DT
DTL
CKL
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 31-3 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CKx  (DTx hold time)
Data Hold after CKx  (DTx hold time)
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
Preliminary
121
PIC18F87K22 FAMILY
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
Max
ns
ns
40
20
20
Units
ns
ns
ns
DS39960B-page 519
Conditions
Conditions