AT32UC3B1128-Z1UR Atmel, AT32UC3B1128-Z1UR Datasheet - Page 139
AT32UC3B1128-Z1UR
Manufacturer Part Number
AT32UC3B1128-Z1UR
Description
MCU AVR32 128K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1128-Z1UR
Package / Case
48-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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15. HSB Bus Matrix (HMATRIX)
15.1
15.2
15.3
15.3.1
15.4
15.4.1
32059J–12/2010
Features
Overview
Product Dependencies
Functional Description
Clocks
Special Bus Granting Mechanism
Rev: 2.3.0.2
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The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the HMATRIX before disabling the clock, to avoid freezing the HMATRIX in an undefined
state.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
User Interface on peripheral bus
Configurable Number of Masters (Up to sixteen)
Configurable Number of Slaves (Up to sixteen)
One Decoder for Each Master
Programmable Arbitration for Each Slave
Programmable Default Master for Each Slave
One Cycle Latency for the First Access of a Burst
Zero Cycle Latency for Default Master
One Special Function Register for Each Slave (Not dedicated)
– Round-Robin
– Fixed Priority
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
AT32UC3B
139
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