AT32UC3B1128-Z1UR Atmel, AT32UC3B1128-Z1UR Datasheet - Page 646
AT32UC3B1128-Z1UR
Manufacturer Part Number
AT32UC3B1128-Z1UR
Description
MCU AVR32 128K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1128-Z1UR
Package / Case
48-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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31.1.1.4
31.1.1.5
31.1.1.6
31.1.1.7
32059J–12/2010
USB
ADC
PDCA
SSC
1. Additional delay on TD output
2. TF output is not correct
3. Frame Synchro and Frame Synchro Data are delayed by one clock cycle.
1. For isochronous pipe, the INTFRQ is irrelevant
1. Sleep Mode activation needs additional A to D conversion
1. Wrong PDCA behavior when using two PDCA channels with the same PID
Fix/Workaround
Disable the OSC0 through the Power Manager (PM) before going to any sleep mode where
the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1Mohm resistor.
A delay from 2 to 3 system clock cycles is added to TD output when:
TCMR.START = Receive Start,
TCMR.STTDLY = more than ZERO,
RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge,
RFMR.FSOS = None (input).
Fix/Workaround
None.
TF output is not correct (at least emitted one serial clock cycle later than expected) when:
TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer
TCMR.START = Receive start
RFMR.FSOS = None (Input)
RCMR.START = any on RF (edge/level)
Fix/Workaround
None.
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
Clock is CKDIV
The START is selected on either a frame synchro edge or a level,
Frame synchro data is enabled,
Transmit clock is gated on output (through CKO field).
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) whenSTART con-
dition is performed on a generated frame synchro.
IN and OUT tokens are sent every 1 ms (Full Speed).
Fix/Workaround
For longer polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
Wrong PDCA behavior when using two PDCA channels with the same PID.
Fix/Workaround
AT32UC3B
646
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