DSPIC30F1010-20E/SP Microchip Technology, DSPIC30F1010-20E/SP Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F1010-20E/SP
• Description: IC DSPIC MCU/DSP 6K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-20E/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 15MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 6KB
• Supply Voltage Range: 3V To 5.5V
• Package: 28SPDIP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 1-2:
© 2006 Microchip Technology Inc.
OSC1/CLK1
Control Signals
to Various Blocks
Program Memory
Controller
Address Latch
Interrupt
Data Latch
(12 Kbytes)
Comparator
Module
SPI1
24
Generation
Timing
Instruction
Decode &
Control
16
MCLR
24
24
Control Block
PSV & Table
Data Access
24
10-bit ADC
dsPIC30F2020 BLOCK DIAGRAM
Timers
16
Control
Start-up Timer
Stack
Logic
PCU
Program Counter
Watchdog
Power-up
Oscillator
Y Data Bus
Timer
Reset
Timer
POR
8
ROM Latch
Notification
PCH
Capture
Module
Change
IR
Input
Input
Control
Logic
Loop
16
PCL
Decode
16
Engine
DSP
16
Compare
Module
Output
SMPS
PWM
Data Latch
(256 bytes)
Y AGU
Address
Y Data
Effective Address
Preliminary
Latch
RAM
16
16
16
W Reg Array
16
ALU<16>
16 x 16
16
16
16
X RAGU
X WAGU
X Data Bus
16
Data Latch
(256 bytes)
Divide
UART1
Unit
Address
X Data
I
Latch
2
RAM
C™
16
16
16
dsPIC30F1010/202X
16
PORTA
PORTD
PORTE
PORTF
PORTB
U1ATX/CN1/RE7
PGD2/EMUD2/SCK1/SFLT3/OC2/
INT2/RF6
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/SFLT1/IC1/
INT1/RD0
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PGC1/EMUC1/EXTREF/PWM4L/
T1CK/
PGD1/EMUD1/PWM4H/T2CK/
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/
OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/
OSC2/CLKO/RB7
U1ARX/CN0/RE6
DS70178C-page 13