PIC18F2320-E/SP Microchip Technology, PIC18F2320-E/SP Datasheet - Page 26

• Manufacturer Part Number: PIC18F2320-E/SP
• Description: IC MCU FLASH 4KX16 EEPROM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
2.6.3
The internal oscillator block is calibrated at the factory
to produce an INTRC output frequency of approxi-
mately 31 kHz. (See parameters F20 and F21 in
Table 26-8.)
The INTRC frequency can be adjusted two ways:
• If TUNSEL (OSCTUN2<7>) is clear –
• If TUNSEL (OSCTUN2<7>) is set – TUN5:TUN1
REGISTER 2-2:
DS39599G-page 24
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-1
bit 0
TUN5:TUN1 in OSCTUNE<5:1> adjusts the
INTRC clock frequency and also can adjust the
INTOSC clock frequency. (See Register 2-1,
OSCTUNE.)
in OSCTUN2<5:1> adjusts the INTRC clock fre-
quency without affecting the INTOSC frequency.
(See Register 2-2, OSCTUN2.)
TUNSEL
R/W-0
OSCTUN2 REGISTER
TUNSEL: Enables tuning of INTRC using OCSTUN2<5:1>
1 = INTRC adjusted by OSCTUN2<5:1>
0 = INTRC adjusted by OSCTUNE<5:1>
Unimplemented: Read as ‘0’
TUN<5:1>: Frequency Tuning bits – Adjusts the frequency of INTRC when TUNSEL is set
011111 = Maximum frequency
•
•
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
100000 = Minimum frequency
TUN<0>: A placeholder with no effect on the INTRC frequency. Provided to facilitate incrementation
and decrementation of the OSCTUN2 register and adjustment of the INTRC frequency.
U-0
—
OSCTUN2: INTRC OSCILLATOR TUNING REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN5
•
•
•
•
R/W-0
TUN4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
TUN3
In OSCTUN2, the OSCTUN2<0> bit has no effect, but
is readable and writable, enabling changes of the
INTRC frequency using two increment or decrement
instructions.
When the OSCTUN2 register is modified, the INTRC
frequency will begin shifting to the new frequency, and
will stabilize at the new frequency within 100 μs. Code
execution continues during this shift.
There is no indication when the shift occurs. Operation
of features that depend on the INTRC clock source fre-
quency also will be affected by the change in fre-
quency. This includes the WDT, Fail-Safe Clock
Monitor and peripherals.
R/W-0
TUN2
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
TUN1
R/W-0
TUN0
bit 0