ATMEGA325A-MU Atmel, ATMEGA325A-MU Datasheet - Page 64
![IC MCU AVR 32K FLASH 64VQFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA325A-MU
Manufacturer Part Number
ATMEGA325A-MU
Description
IC MCU AVR 32K FLASH 64VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA325A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.2
12.2.1
12.2.2
64
Register Description
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
EICRA – External Interrupt Control Register A
EIMSK – External Interrupt Mask Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-1.
• Bit 7 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT30:24 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3
Interrupt Vector. PCINT30:24 pins are enabled individually by the PCMSK3 Register.
Note:
• Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
Note:
Bit
(0x69)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
ISC01
0
0
1
1
1. This bit is a reserved bit in
1. This bit is a reserved bit in
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and
should always be written to zero.
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and
should always be written to zero.
Interrupt 0 Sense Control
PCIE3
ISC00
R
7
–
0
R
7
0
0
1
0
1
(1)
PCIE2
Table
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
6
–
0
R
6
0
(1)
12-1. The value on the INT0 pin is sampled before detecting
PCIE1
R/W
R
5
–
0
5
0
PCIE0
R/W
R
4
–
0
4
0
3
–
R
0
R
3
–
0
2
–
R
0
R
2
–
0
ISC01
R/W
1
0
R
1
–
0
ISC00
R/W
INT0
R/W
0
0
0
0
8285B–AVR–03/11
EICRA
EIMSK
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