PIC18F4220-E/P Microchip Technology, PIC18F4220-E/P Datasheet - Page 111
![IC MCU FLASH 2KX16 EEPROM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4220-E/P
Manufacturer Part Number
PIC18F4220-E/P
Description
IC MCU FLASH 2KX16 EEPROM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4220-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F1320-ISS PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- Current page: 111 of 394
- Download datasheet (7Mb)
10.4
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory mapped.
Read-modify-write operations on the LATD register read
and write the latched output value for PORTD.
All pins on PORTD are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
FIGURE 10-11:
© 2007 Microchip Technology Inc.
Note:
Note:
PORTD, TRISD and LATD
Registers
PORTD is only available on PIC18F4X20
devices.
On a Power-on Reset, these pins are
configured as digital inputs.
PORTD/CCP1 Select
CCP Data Out
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
RD PORTD
WR TRISD
PSP Read
RD TRISD
PSP Write
Note 1:
BLOCK DIAGRAM OF RD7:RD5 PINS
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
PIC18F2220/2320/4220/4320
0
1
DD
and V
0
1
Q
SS
.
EN
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4:
EN
CLRF
CLRF
MOVLW
MOVWF
0
1
D
Note:
PORTD
LATD
0xCF
TRISD
1
0
When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
TTL Buffer
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
: Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
V
N
V
Schmitt Trigger
Input Buffer
P
INITIALIZING PORTD
DD
SS
DS39599G-page 109
I/O pin
(1)
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