PIC18F4220-E/P Microchip Technology, PIC18F4220-E/P Datasheet - Page 180
![IC MCU FLASH 2KX16 EEPROM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4220-E/P
Manufacturer Part Number
PIC18F4220-E/P
Description
IC MCU FLASH 2KX16 EEPROM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4220-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F1320-ISS PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- Current page: 180 of 394
- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
17.4.5
The addressing procedure for the I
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is com-
pared against the SSPADD. It is also compared to the
general call address and fixed in hardware.
FIGURE 17-15:
DS39599G-page 178
GCEN (SSPCON2<7>)
SSPOV (SSPCON1<6>)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
Call
GENERAL CALL ADDRESS
SUPPORT
Enable
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
bit
1
(GCEN)
2
General Call Address
2
C bus is such that
3
2
4
C protocol. It
is
5
enabled
6
7
R/W = 0
8
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
ACK
Address is compared to general call address
after ACK, set interrupt
9
D7
1
D6
2
Cleared in software
SSPBUF is read
Receiving Data
D5
3
D4
4
© 2007 Microchip Technology Inc.
D3
5
D2
6
D1
7
D0
8
ACK
9
‘0’
‘1’
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