ATXMEGA128A1-C7U Atmel, ATXMEGA128A1-C7U Datasheet - Page 61
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ATXMEGA128A1-C7U
Manufacturer Part Number
ATXMEGA128A1-C7U
Description
MCU AVR 128K FLASH 1.6V 100VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet
1.ATAVRONEKIT.pdf
(113 pages)
Specifications of ATXMEGA128A1-C7U
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-VFBGA
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
8 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
78
Number Of Timers
8
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT, ATQT600
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
8067M–AVR–09/10
Mnemonics
CALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
MOV
MOVW
LDI
LDS
LD
LD
LD
LD
LD
Operands
k
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
A, b
A, b
s, k
s, k
Rd, Rr
Rd, Rr
Rd, K
Rd, k
Rd, X
Rd, X+
Rd, -X
Rd, Y
Rd, Y+
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Description
call Subroutine
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Copy Register
Copy Register Pair
Load Immediate
Load Direct from data space
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Data Transfer Instructions
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (N ⊕ V= 0) then PC
if (N ⊕ V= 1) then PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (C = 0) then PC
if (N = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (Rd = Rr) PC
Rd - Rr - C
X ← X - 1,
Rd ← (X)
Rd ← (Y)
Rd+1:Rd
Rd - Rr
Rd - K
Operation
PC
PC
PC
Rd
Rd
Rd
Rd
Rd
Rd
X
Y
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
k
STACK
STACK
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
Rr
Rr+1:Rr
K
(k)
(X)
(X)
X + 1
X - 1
(X)
(Y)
(Y)
Y + 1
XMEGA A1
Flags
None
None
I
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
3 / 4
4 / 5
4 / 5
2
1
1
2
1
1
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
1
1
1
1
1
1
(1)
(1)
(1)
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