ATMEGA64-16MUR Atmel, ATMEGA64-16MUR Datasheet - Page 104

• Manufacturer Part Number: ATMEGA64-16MUR
• Description: MCU AVR 64KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-bit
Timer/Counter
Register
Description
TCCR0 –
Timer/Counter Control
Register
2490Q–AVR–06/10
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR0 is written when
operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare
Match is forced on the waveform generation unit. The OC0 output is changed according to its
COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the
value present in the COM01:0 bits that determines the effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
page
Table 52. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set
in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0
bit setting.
Normal or CTC mode (non-PWM).
Bit
0x33 (0x53)
Read/Write
Initial Value
Mode
0
1
2
3
98.
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
WGM01
(CTC0)
Table 53
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
FOC0
W
7
0
WGM00
(PWM0)
shows the COM01:0 bit functionality when the WGM01:0 bits are set to a
WGM00
0
1
0
1
R/W
6
0
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
COM01
R/W
5
0
COM00
R/W
4
0
WGM01
R/W
3
0
(1)
TOP
0xFF
OCR0
0xFF
0xFF
CS02
R/W
Table 52
2
0
Update of
OCR0 at
Immediate
TOP
Immediate
BOTTOM
CS01
R/W
1
0
and
ATmega64(L)
“Modes of Operation” on
CS00
R/W
0
0
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
TCCR0
104