ATMEGA64-16MUR Atmel, ATMEGA64-16MUR Datasheet - Page 306

• Manufacturer Part Number: ATMEGA64-16MUR
• Description: MCU AVR 64KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Serial
Programming Pin
Mapping
SPI Serial
Programming
Algorithm
2490Q–AVR–06/10
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important
difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not
used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-
ming mode as shown in
Table 127. Pin Mapping SPI Serial Programming
Figure 147. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega64, data is clocked on the rising edge of SCK.
When reading data from the ATmega64, data is clocked on the falling edge of SCK. See
148
To program and verify the ATmega64 in the SPI Serial Programming mode, the following
sequence is recommended:
1. Power-up sequence:
Apply power between V
tems, the programmer cannot guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
for timing details.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7V - 5.5V.
MISO (PDO)
MOSI (PDI)
Symbol
XTAL1 pin.
SCK
Table
CC
127.
and GND while RESET and SCK are set to “0”. In some sys-
MOSI
MISO
ck
ck
SCK
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Pins
PE0
PE1
PB1
PE0
PE1
PB1
XTAL1
RESET
GND
I/O
(1)
O
I
I
AVCC
VCC
+2.7 - 5.5V
+2.7 - 5.5V
(2)
Serial Data Out
Serial Data In
Description
Serial Clock
ck
ck
ATmega64(L)
≥ 12 MHz
≥ 12 MHz
Figure
306