PIC16LC67-04I/PT Microchip Technology, PIC16LC67-04I/PT Datasheet - Page 58

• Manufacturer Part Number: PIC16LC67-04I/PT
• Description: IC MCU OTP 8KX14 PWM 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC67-04I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PIC16C6X
5.5
PORTE has three pins, RE2/CS, RE1/WR, and
RE0/RD which are individually configurable as inputs
or outputs. These pins have Schmitt Trigger input buff-
ers.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). In this mode the input buffers are TTL.
Figure 5-9 shows the TRISE register, which controls
the parallel slave port operation and also controls the
direction of the PORTE pins.
FIGURE 5-9:
DS30234D-page 58
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
bit7
bit 7 :
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R-0
IBF
PORTE and TRISE Register
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
Unimplemented: Read as '0'
PORTE Data Direction Bits
Bit2: Direction Control bit for pin RE2/CS
1 = Input
0 = Output
Bit1: Direction Control bit for pin RE1/WR
1 = Input
0 = Output
Bit0: Direction Control bit for pin RE0/RD
1 = Input
0 = Output
OBF
R-0
TRISE REGISTER (ADDRESS 89h)
R/W-0
IBOV
PSPMODE
R/W-0
U-0
—
R/W-1
bit2
FIGURE 5-8:
Note 1: I/O pins have protection diodes to V
R/W-1
bit1
Data
bus
WR
TRIS
WR
PORT
RD PORT
R/W-1
TRIS Latch
Data Latch
bit0
D
D
CK
CK
bit0
RD TRIS
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
Q
Q
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1997 Microchip Technology Inc.
Q
read as ‘0’
EN
Schmitt
Trigger
input
buffer
EN
D
DD
I/O pin
and V
SS
(1)
.