PIC16LC67-04I/PT Microchip Technology, PIC16LC67-04I/PT Datasheet - Page 79

• Manufacturer Part Number: PIC16LC67-04I/PT
• Description: IC MCU OTP 8KX14 PWM 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC67-04I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

10.1.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 10-1: CHANGING BETWEEN
CLRF
MOVLW
MOVWF
10.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time interrupt flag bit CCP1IF is set.
FIGURE 10-3: COMPARE MODE
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
RC2/CCP1
1997 Microchip Technology Inc.
Output Enable
TRISC<2>
CCP1CON
NEW_CAPT_PS ; Load the W reg with
CCP1CON
CCP PRESCALER
Compare Mode
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>).
Q
CCP1CON<3:0>
Special Event Trigger
OPERATION BLOCK
DIAGRAM
R
Mode Select
S
CAPTURE PRESCALERS
Output
; Turn CCP module off
; the new prescaler
; mode value and CCP ON
; Load CCP1CON with
; this value
Logic
Set CCP1IF
PIR1<2>
match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
10.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
10.2.1
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.2
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
10.2.3
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 and CCP2
resets the TMR1 register pair. This allows the
CCPR1H:CCPR1L and CCPR2H:CCPR2L registers to
effectively be 16-bit programmable period register(s)
for Timer1.
For compatibility issues, the special event trigger out-
put of CCP1 (PIC16C72) and CCP2 (all other
PIC16C7X devices) also starts an A/D conversion.
Note:
Note:
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The “special event trigger” from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
PIC16C6X
DS30234D-page 79