ATMEGA169PV-8MU Atmel, ATMEGA169PV-8MU Datasheet - Page 243
ATMEGA169PV-8MU
Manufacturer Part Number
ATMEGA169PV-8MU
Description
IC AVR MCU 16K 8MHZ 1.8V 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169PV-8MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/USART/USI
Total Internal Ram Size
1KB
# I/os (max)
54
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
MLF EP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA169PV-8MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA169PV-8MUR
Manufacturer:
LISHENG
Quantity:
1 000
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23.4.2
8018P–AVR–08/10
Updating the LCD
Note:
Before a re-initialization is done, the LCD controller/driver should be disabled.
Display memory (LCDDR0, LCDDR1, ..), LCD Blanking (LCDBL), Low power waveform
(LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There are no
restrictions on writing these LCD Register locations, but an LCD data update may be split
between two frames if data are latched while an update is in progress. To avoid this, an interrupt
routine can be used to update Display memory, LCD Blanking, Low power waveform, and con-
trast control, just after data are latched.
Assembly Code Example
C Code Example
LCD_Init:
Void LCD_Init(void);
{
}
; Use 32 kHz crystal oscillator
; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins
ldi
sts
; Using 16 as prescaler selection and 7 as LCD Clock Divide
; gives a frame rate of 49 Hz
ldi
sts
; Set segment drive time to 125 µs and output voltage to 3.3 V
ldi
sts
; Enable LCD, default waveform and no interrupt enabled
ldi
sts
ret
/* Use 32 kHz crystal oscillator */
/* 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins */
LCDCRB = (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2);
/* Using 16 as prescaler selection and 7 as LCD Clock Divide */
/* gives a frame rate of 49 Hz */
LCDFRR = (1<<LCDCD2) | (1<<LCDCD1);
/* Set segment drive time to 125 µs and output voltage to 3.3 V*/
LCDCCR = (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1);
/* Enable LCD, default waveform and no interrupt enabled */
LCDCRA = (1<<LCDEN);
1.
See ”About Code Examples” on page 10.
r16, (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2)
LCDCRB, r16
r16, (1<<LCDCD2) | (1<<LCDCD1)
LCDFRR, r16
r16, (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1)
LCDCCR, r16
r16, (1<<LCDEN)
LCDCRA, r16
(1)
(1)
ATmega169P
243
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