DSPIC30F2023-30I/ML Microchip Technology, DSPIC30F2023-30I/ML Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F2023-30I/ML
• Description: IC DSPIC MCU/DSP 12K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Package: 44QFN EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.0
7.1
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
is described in
Commands”. The response set is described in
Section 9.0 “Programming Executive
7.2
The Enhanced ICSP interface is a 2-wire SPI interface
implemented using the PGC and PGD pins. The PGC
pin is used as a clock input pin, and the clock source
must be provided by the programmer. The PGD pin is
used for sending command data to, and receiving
response data from the programming executive. All
serial data is transmitted on the rising edge of PGC and
is latched on the falling edge of PGC. All data
transmissions are sent to the Most Significant bit first,
using 16-bit mode (see
FIGURE 7-1:
© 2010 Microchip Technology Inc.
PGC
PGD
MSb
1
PROGRAMMER –
PROGRAMMING EXECUTIVE
COMMUNICATION
Communication Overview
Communication Interface and
Protocol
P1a
P1b
2
14 13 12 11
3
Section 8.0 “Programming Executive
P1
4
5
PROGRAMMING
EXECUTIVE SERIAL
TIMING
Figure
6
...
11
7-1).
5
P2
12
4
13
3
Responses”.
14
2
P3
15 16
1
LSb
Since a 2-wire SPI interface is used, and data
transmissions are bidirectional, a simple protocol is
used to control the direction of PGD. When the
programmer completes a command transmission, it
releases the PGD line and allows the programming
executive to drive this line high. The programming
executive keeps the PGD line high to indicate that it is
processing the command.
After the programming executive has processed the
command, it brings PGD low for 15 μsec to indicate to
the programmer that the response is available to be
clocked out. The programmer can begin to clock out
the response 20 μsec after PGD is brought low, and it
must provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
Once the entire response is clocked out, the
programmer should terminate the clock on PGC until it
is time to send another command to the programming
executive. This protocol is illustrated in
7.3
In Enhanced ICSP mode, the dsPIC30F SMPS
operates from the fast internal RC oscillator FRC,
which has a nominal frequency of 10 or 15 MHz. This
oscillator frequency yields an effective system clock
frequency of 2.5 or 3.75 MHz. Since the SPI module
operates in Slave mode, the programmer must limit the
SPI clock rate to a frequency not greater than 1 MHz.
7.4
The programming executive uses no Watchdog Timer
or time out for transmitting responses to the
programmer. If the programmer does not follow the flow
control mechanism using PGC, as described in
Section 7.2 “Communication Interface and Proto-
col”, it is possible that the programming executive will
behave unexpectedly while trying to send a response
to the programmer. Since the programming executive
has no time out, it is imperative that the programmer
correctly follow the described communication protocol.
As a safety measure, the programmer should use the
command time outs identified in
command time out expires, the programmer should
reset
programming the device again.
Note:
the
SPI Rate
Time Outs
If the programmer provides the SPI with a
clock faster than 1 MHz, the behavior of
the
unpredictable.
programming
programming
executive
executive
DS70284C-page 15
Table
Figure
8-1. If the
and
will
7-2.
start
be