AT89C51RE2-RLTUM Atmel, AT89C51RE2-RLTUM Datasheet - Page 42

• Manufacturer Part Number: AT89C51RE2-RLTUM
• Description: MCU 8051 128K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Height: 1.45 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10.1 mm
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Writing the Flash
Spaces
User
42
AT89C51RE2
Figure 13. Column Latches Loading Procedure
Note:
Note:
Note:
The following procedure is used to program the User space and is summarized in Figure 14:
•
•
•
•
Load up to one page of data in the column latches from address 0000h to FFFFh (see
Figure 13.).
Disable the interrupts.
Launch the programming by writing the data sequence 50h followed by A0h in FCON
register.
The end of the programming indicated by the FBUSY flag cleared.
Enable the interrupts.
The last page address used when loading the column latch is the one used to select the page pro-
gramming address.
The value of MB02:0 during the last load gives the upper 32K bytes bank target selection.
The execution of this sequence when BUSY flag is set leads to the no-execution of the write in the
column latches (the previous loaded data remains unchanged).
Exec: MOVX @DPTR, A
Column Latches Reset
Data memory Mapping
FCON = 00h (FPS = 0)
Restore IT and default
FCON= ABh (FPS=1)
FCON= 53h (FPS=0)
target memory bank
Column Latches
Select target bank
Save & Disable IT
DPTR= Address
Last Byte
ACC= Data
MB2:0=YY
Data Load
Loading
to load?
EA= 0
7663E–8051–10/08