ATMEGA1280-16AUR Atmel, ATMEGA1280-16AUR Datasheet - Page 209

• Manufacturer Part Number: ATMEGA1280-16AUR
• Description: MCU AVR 128K FLASH 16MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1280-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.2.4
21.3
2549M–AVR–09/10
Frame Formats
Synchronous Clock Operation
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 21-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 21-4 on page 210
brackets are optional.
1 start bit.
5, 6, 7, 8, or 9 data bits.
no, even or odd parity bit.
1 or 2 stop bits.
UCPOL = 1
UCPOL = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
RxD / TxD
RxD / TxD
XCK
XCK
Figure 21-3
illustrates the possible combinations of the frame formats. Bits inside
ATmega640/1280/1281/2560/2561
shows, when UCPOLn is zero the data will be changed at
f
XCK
<
f
---------- -
OSC
4
Sample
Sample
209