AT91SAM9G46-CU Atmel, AT91SAM9G46-CU Datasheet
AT91SAM9G46-CU
Specifications of AT91SAM9G46-CU
Related parts for AT91SAM9G46-CU
AT91SAM9G46-CU Summary of contents
Page 1
... Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm AT91SAM ARM-based Embedded MPU SAM9G46 Preliminary Summary NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. 11028CS–ATARM–8-Apr-11 ...
Page 2
Description The ARM926EJ-S based SAM9G46 features the frequently requested combination of user inter- face functionality and high data rate connectivity, including LCD Controller, resistive touch- screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the ...
Page 3
Block Diagram Figure 2-1. SAM9G46 Block Diagram 11028CS–ATARM–8-Apr-11 PIO SAM9G46 3 ...
Page 4
Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIOM0 DDR2 I/O Lines Power Supply VDDIOM1 EBI I/O Lines Power Supply VDDIOP0 Peripherals I/O Lines Power Supply VDDIOP1 Peripherals I/O Lines Power Supply VDDIOP2 ISI I/O ...
Page 5
Table 3-1. Signal Description List (Continued) Signal Name Function SHDN Shut-Down Control WKUP Wake-Up Input TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock NRST Microcontroller Reset ...
Page 6
Table 3-1. Signal Description List (Continued) Signal Name Function PC0 - PC31 Parallel IO Controller C PD0 - PD31 Parallel IO Controller D PE0 - PE31 Parallel IO Controller E DDR_D0 - Data Bus DDR_D15 DDR_A0 - Address Bus DDR_A13 ...
Page 7
Table 3-1. Signal Description List (Continued) Signal Name Function CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 -CFCS1 CompactFlash Chip Select Lines NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable SDCK,#SDCK ...
Page 8
Table 3-1. Signal Description List (Continued) Signal Name Function AC97RX AC97 Receive Signal AC97TX AC97 Transmit Signal AC97FS AC97 Frame Synchronization Signal AC97CK AC97 Clock signal TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A ...
Page 9
Table 3-1. Signal Description List (Continued) Signal Name Function ETXCK Transmit Clock or Reference Clock ERXCK Receive Clock ETXEN Transmit Enable ETX0-ETX3 Transmit Data ETXER Transmit Coding Error ERXDV Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier ...
Page 10
Table 3-1. Signal Description List (Continued) Signal Name Function Analog input channel 3 or AD3Y M Touch Screen Left channel GPAD4-GPAD7 Analog Inputs TSADTRG ADC Trigger TSADVREF ADC Reference Notes: 1. Refer to peripheral multiplexing tables in 2. When configured ...
Page 11
Package and Pinout The SAM9G46 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 Figure 4-1. 11028CS–ATARM–8-Apr-11 shows the orientation of the 324-ball TFBGA Package Orientation of the 324-ball TFBGA Package ...
Page 12
TFBGA Package Pinout Table 4-1. SAM9G46 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 ...
Page 13
Table 4-1. SAM9G46 Pinout for 324-ball BGA Package (Continued) Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 ...
Page 14
Power Considerations 5.1 Power Supplies The SAM9G46 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. • VDDIOM0 ...
Page 15
Processor and Architecture 6.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with DSP Instruction Extensions and Jazelle • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
Page 16
Bus Matrix • 12-layer Matrix, handling requests from 11 masters • Programmable Arbitration strategy – Fixed-priority Arbitration – Round-Robin Arbitration, either with no default master, last accessed default master • Burst Management – Breaking with Slot Cycle Limit Support ...
Page 17
Matrix Slaves Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 6.2.3 Masters to ...
Page 18
Figure 6-1. Table 6-3. SAM9G46 Masters to Slaves Access DDRMP_DIS = 0 Master 0 ARM ARM Slave 926 Instr. 926 Data 0 Internal SRAM 0 X Internal ROM X UHP OHCI X UHP EHCI X LCD User Int. X UDPHS ...
Page 19
Table 6-4. SAM9G46 Masters to Slaves Access with DDRMP_DIS = 1 (default) Master 0 ARM Slave 926 Instr. 926 Data 0 Internal SRAM 0 X Internal ROM X UHP OHCI X UHP EHCI X 1 LCD User Int. X UDPHS ...
Page 20
The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): Table 6-6. Instance name DBGU USART3 USART2 USART1 USART0 AC97C TDES SHA SPI1 SPI0 SSC1 SSC0 TSADCC DBGU USART3 USART2 ...
Page 21
Figure 6-2. 6.5 DMA Controller • Two Masters • Embeds 8 channels • 64 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation at End of Transfer • Word, HalfWord, Byte transfer support. • memory to ...
Page 22
Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug ...
Page 23
Memories Figure 7-1. SAM9G46 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 256M Bytes 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ 256M Bytes DDRSDRC1 0x2FFF FFFF 0x3000 ...
Page 24
Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 ...
Page 25
Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in the Chip Configuration User Interface. This SRAM ...
Page 26
BMS = 1, boot on embedded ROM The system boots on Boot Program. • Boot on on-chip RC • Enable the 32768 Hz oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into ...
Page 27
External Memories The SAM99G46 features a Multi-port DDR2 Interface and an External Bus Interface allowing to connect to a wide range of external memories and to any parallel peripheral. 7.3.1 DDRSDRC0 Multi-port DDRSDR Controller Four AHB Interfaces, Management of ...
Page 28
Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash 7.3.2.1 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or ...
Page 29
ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or ...
Page 30
System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...
Page 31
System Controller Block Diagram Figure 8-1. SAM9G46 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN ...
Page 32
Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU ...
Page 33
Figure 8-2. 8.6 Slow Clock Selection The SAM9G46 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an ...
Page 34
Figure 8-3. After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSC- SEL = 0 allowing the system to start on the internal RC oscillator. The programmer controls by software the slow ...
Page 35
Switch from 32768 Hz oscillator to internal RC oscillator by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32768Hz oscillator by setting the bit OSC32EN to 0. 8.7 Power ...
Page 36
Figure 8-4. PLLACK /1,/2 8.7.1 Main Application Modes The Power Management Controller provides 3 main application modes. 8.7.1.1 Normal Mode • PLLA and UPLL are running respectively at 400 MHz and 480 MHz • USB Device High Speed and Host ...
Page 37
No UDP HS, UHP FS and DDR2 Mode • Only PLLA is running at 384 MHz, UPLL power consumption is saved • USB Device High Speed and Host EHCI High Speed operations are NOT allowed • Full Speed OHCI ...
Page 38
... Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...
Page 39
PIO Controllers • 5 PIO Controllers, PIOA, PIOB, PIOC, PIOD and PIOE, controlling a maximum of 160 I/O Lines • Each PIO Controller controls programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has ...
Page 40
Peripherals 9.1 Peripheral Mapping As shown in space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. 9.2 Peripheral Identifiers Table 9-1 for the control of the peripheral interrupt with ...
Page 41
Table 9-1. SAM9G46 Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic 29 MCI1 30 Reserved 31 AIC 9.3 Peripheral Interrupts and Clock Control 9.3.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: ...
Page 42
PIO Controller A Multiplexing Table 9-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A PA0 MCI0_CK PA1 MCI0_CDA PA2 MCI0_DA0 PA3 MCI0_DA1 PA4 MCI0_DA2 PA5 MCI0_DA3 PA6 MCI0_DA4 PA7 MCI0_DA5 PA8 MCI0_DA6 PA9 MCI0_DA7 PA10 ETX0 PA11 ...
Page 43
PIO Controller B Multiplexing Table 9-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A PB0 SPI0_MISO PB1 SPI0_MOSI PB2 SPI0_SPCK PB3 SPI0_NPCS0 PB4 TXD1 PB5 RXD1 PB6 TXD2 PB7 RXD2 PB8 TXD3 PB9 RXD3 PB10 TWD1 PB11 ...
Page 44
PIO Controller C Multiplexing Table 9-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 DQM2 PC1 DQM3 PC2 A19 PC3 A20 PC4 A21/NANDALE PC5 A22/NANDCLE PC6 A23 PC7 A24 PC8 CFCE1 PC9 CFCE2 PC10 NCS4/CFCS0 PC11 ...
Page 45
PIO Controller D Multiplexing Table 9-5. Multiplexing on PIO Controller D (PIOD) I/O Line Peripheral A PD0 TK0 PD1 TF0 PD2 TD0 PD3 RD0 PD4 RK0 PD5 RF0 PD6 AC97RX PD7 AC97TX PD8 AC97FS PD9 AC97CK PD10 TD1 PD11 ...
Page 46
PIO Controller E Multiplexing Table 9-6. Multiplexing on PIO Controller E (PIOE) I/O Line Peripheral A PE0 LCDPWR LCDMOD PE1 LCDCC PE2 PE3 LCDVSYNC PE4 LCDHSYNC PE5 LCDDOTCK PE6 LCDDEN PE7 LCDD0 PE8 LCDD1 PE9 LCDD2 PE10 LCDD3 PE11 ...
Page 47
Embedded Peripherals 10.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial ...
Page 48
Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards ...
Page 49
AC97 Controller • Compatible with AC97 Component Specification V2.2 • Capable to Interface with a Single Analog Front end • Three independent RX Channels and three independent TX Channels – One RX and one TX channel dedicated to the ...
Page 50
Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with Memory Stick PRO • Compatibility with CE ATA 10.9 USB High Speed Host Port (UHPHS) • Compliant with Enhanced HCI Rev ...
Page 51
Touch Screen Analog-to-Digital Converter (TSADC) • 8-channel ADC • Support 4-wire resistive Touch Screen • 10-bit 384 Ksamples/sec. Successive Approximation Register ADC • -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 8-to-1 multiplexer, offering eight ...
Page 52
Preview scaler to generate smaller size image 10.15 8-channel DMA (DMA) • Acting as two Matrix Masters • Embeds 8 unidirectional channels with programmable priority • Address Generation – Source/Destination address programming – Address increment, decrement or no change ...
Page 53
Cryptographic Key • 16 Clock Cycles Encryption/Decryption Processing Time with a 256-bit Cryptographic Key • Support of the Five Standard Modes of Operation Specified in the NIST Special Publication 800- 38A, Recommendation for Block Cipher Modes of Operation ...
Page 54
Clock Cycles to Maximize the Bandwidth for SHA1 or 386 Clock Cycles or Other Applications in PDC (Peripheral DMA) – 72 Clock Cycles to Maximize the Bandwidth for SHA256 or 265 Clock Cycles or Other Applications in PDC ...
Page 55
Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 324-ball TFBGA Package Drawing 11028CS–ATARM–8-Apr-11 SAM9G46 55 ...
Page 56
... SAM9G46 Ordering Information Table 12-1. AT91SAM9G46 Ordering Information Ordering Code AT91SAM9G46-CU SAM9G46 56 Package Package Type TFBGA324 Green Temperature Operating Range Industrial -40°C to 85°C 11028CS–ATARM–8-Apr-11 ...
Page 57
Revision History Doc. Rev Comments Introduction Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9G46 11028CS Section 5.1 “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to ...
Page 58
SAM9G46 58 11028CS–ATARM–8-Apr-11 ...
Page 59
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...