AT91SAM9G46-CU Atmel, AT91SAM9G46-CU Datasheet - Page 35

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AT91SAM9G46-CU

Manufacturer Part Number
AT91SAM9G46-CU
Description
IC ARM9 MCU 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9G46-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
8.7
11028CS–ATARM–8-Apr-11
Power Management Controller
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
PMC output clocks
Note:
This allows the software control of five flexible operating modes:
• Switch from 32768 Hz oscillator to internal RC oscillator by setting the bit OSCSEL to 0.
• Wait 5 slow clock cycles for internal resynchronization.
• Disable the 32768Hz oscillator by setting the bit OSC32EN to 0.
• UPLLCK: From UTMI PLL
• PLLACK From PLLA
• SLCK: slow clock from OSC32K or internal RC OSC
• MAINCK: from 12 MHz external oscillator
• Processor Clock PCK
• Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be
• DDR system clock equal to 2xMCK
• USB Host EHCI High speed clock (UPLLCK)
• USB OHCI clocks (UHP48M and UHP12M)
• Independent peripheral clocks, typically at the frequency of MCK
• Two programmable clock outputs: PCK0 and PCK1
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery
1,2,3 or 4
stopped waiting for an interrupt
DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
SAM9G46
35

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