AT91SAM9G46-CU Atmel, AT91SAM9G46-CU Datasheet - Page 15

• Manufacturer Part Number: AT91SAM9G46-CU
• Description: IC ARM9 MCU 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G46-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6. Processor and Architecture
6.1
11028CS–ATARM–8-Apr-11
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with DSP Instruction Extensions and
• Two Instruction Sets
• 5-Stage Pipeline Architecture:
• 32-KByte Data Cache, 32-KByte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
• TCM Interface
Jazelle
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
each quarter of the page
system flexibility
32-bit data interface
(Words)
®
technology for Java
®
acceleration
SAM9G46
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