DSPIC30F6012T-20E/PF Microchip Technology, DSPIC30F6012T-20E/PF Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F6012T-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012T-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012T20EP

dsPIC30F6011/6012/6013/6014
12. 32-bit General Purpose Timers
13. Output Compare Module
14. 12-bit 100 ksps Analog-to-Digital Converter
15. Data Converter Interface – Slave Mode
16. DCI – Stop in Idle mode
17. CAN SFR Reads
18. High I
19. Regulating Voltage for 5V/30 MIPS Applications
20. dsPIC30F6011/6013 Code Protection
21. 4x PLL Operation
22. Sequential Interrupts
23. 8x PLL Mode
DS80198J-page 2
The 32-bit general purpose timers do not function
as specified for prescaler ratios other than 1:1.
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
(ADC)
The 12-bit ADC scans one channel less than that
specified when configured to perform channel
scanning on MUX A inputs and alternately
converting a fixed MUX B input.
In Slave mode, the DCI module does not function
correctly when data communication is configured
to start one serial clock after the frame
synchronization pulse.
The DCI module should not be stopped when the
device enters Idle mode.
Read operations performed on CAN module
Special Function Registers (SFRs) may yield
incorrect results at operation over 20 MIPS.
Memory
This release of silicon exhibits a current draw (I
of approximately 370 mA during a Row Erase
operation performed on program Flash memory.
For this release of silicon, applications operating
off 5 volts V
V
Addresses in the range 0x6000 through 0xFFFF
may not be code-protected for this revision of
dsPIC30F6011 and dsPIC30F6013 silicon.
The 4x PLL mode of operation may not function
correctly for certain input frequencies.
Sequential interrupts after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may
cause an address error trap.
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
DD
remains within 5% of 5 volts.
DD
During Row Erase of Program Flash
DD
at 30 MIPS should ensure that the
DD
)
24. Sleep Mode
25. I
26. I/O Port – Port Pin Multiplexed with IC1
27. I
28. Timer Module
29. PLL Lock Status Bit
30. PSV Operations
31. I
32. I
33. I
The following sections will describe the erratas and the
work around to these erratas, where they may apply.
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
The I
operating as an I
The port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
least significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
2
2
C™ Module
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
C module loses incoming data bytes when
2
2
C module is enabled, the dsPIC
2
C module is configured as a 10-bit
2
C module is configured for 10-bit
C devices, the A10 and A9 bits may
2
C slave.
© 2008 Microchip Technology Inc.
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