DSPIC30F6012T-20E/PF Microchip Technology, DSPIC30F6012T-20E/PF Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F6012T-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012T-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012T20EP

dsPIC30F6011/6012/6013/6014
9. Module: Interrupt Controller –Traps
EXAMPLE 8:
DS80198J-page 6
.global
__MathError:
Catastrophic accumulator overflow traps are
enabled as follows:
A carry generated out of bit 39 in the accumulator
causes a catastrophic overflow of the accumulator
since the sign bit has been destroyed. If a math
error trap handler has been defined, the processor
will vector to the math error trap handler upon a
catastrophic overflow.
If the respective Accumulator Overflow status bit,
OA or OB (SR<15/14>), is not cleared within the
trap handler routine prior to exiting the trap handler
routine, the processor will immediately re-enter the
trap handler routine.
Work around
If a math error trap occurs due to a catastrophic
accumulator overflow, the overflow status flags,
OA and/or OB (SR<15:14>), should be cleared
within the trap handler routine. Subsequently, the
MATHERR (INTCON1<4>) flag bit should be
cleared within the trap handler prior to executing
the RETFIE instruction.
Since the OA and OB bits are read-only bits, it will
be
accumulator-based instruction within the trap
service routine in order to clear these status bits,
and eventually clear the MATHERR trap flag. This
is shown in Example 8.
- COVTE (INTCON1<8>) = 1
- SATA/SATB (CORCON <7:6>) = 0
necessary
__MathError
BTSC
CLR
BTSC
CLR
BCLR
RETFIE
USING DUMMY DSP
INSTRUCTION
to
SR, #OA
A
SR, #OB
B
INTCON1, #MATHERR
execute
a
dummy
10. Module: Interrupting a
EXAMPLE 9:
EXAMPLE 10:
__T1Interrupt:
__T1Interrupt:
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap:
1. REPEAT loop is active.
2. An interrupt is generated during the execution
3. The CPU executes the Interrupt Service
4. Within the ISR, when the CPU is executing the
Work around
Processing of Interrupt Service Routines should
be disabled while the RETFIE instruction is being
executed. This may be accomplished in two
different ways:
1. Place a DISI instruction immediately before
2. Immediately prior to executing the RETFIE
PUSH
.......
BCLR
POP
DISI
RETFIE
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
of the REPEAT loop.
Routine (ISR) of the source causing the
interrupt.
first instruction cycle of the 3-cycle RETFIE
(Return-from-Interrupt) instruction, a second
interrupt is generated by a source with a higher
interrupt priority.
the RETFIE instruction in all Interrupt Service
Routines of interrupt sources that may be
interrupted by other higher priority interrupt
sources (with priority levels 1 through 6). This
is shown in Example 9 in the Timer1 ISR. In
this example, a DISI instruction inhibits level 1
through level 6 interrupts for 2 instruction
cycles, while the RETFIE instruction is
executed.
instruction, increase the CPU priority level by
modifying the IPL<2:0> (SR<7:5>) bits to ‘111’
as shown in Example 10. This will disable all
interrupts between priority levels 1 through 7.
W0
IFS0, #T1IF
W0
#1
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
;Another interrupt occurs
;here and it is processed
;correctly
;Another interrupt occurs
;here and it is processed
;correctly
DISI BEFORE RETFIE
RAISE IPL BEFORE RETFIE
;Timer1 ISR
;This line optional
;This line optional
;Timer1 ISR
© 2008 Microchip Technology Inc.
REPEAT
Loop