ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 237
![IC MCU 32BIT 256KB FLSH 144LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
ATSAM3U4EA-CU
Manufacturer Part Number
ATSAM3U4EA-CU
Description
IC MCU 32BIT 256KB FLSH 144LFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4EA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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14.4.6.2
14.4.6.3
14.4.7
14.4.7.1
6430D–ATARM–25-Mar-11
IEEE 1149.1 JTAG Boundary Scan
Asynchronous Mode
5.4.3. How to Configure the TPIU
JTAG Boundary-scan Register
The TPIU is configured in asynchronous mode, trace data are output using the single TRAC-
ESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port.
As a consequence, asynchronous trace mode is only available when the Serial Wire Debug
mode is selected since TDO signal is used in JTAG debug mode.
Two encoding formats are available for the single pin output:
This example only concerns the asynchronous trace mode.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when FWUP, NRSTB and JTAGSEL are high
while TST is tied low during power-up and must be kept in this state during the whole boundary
scan operation. The SAMPLE, EXTEST and BYPASS functions are implemented. In
SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies
the processor. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port opera-
tions. A chip reset must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided on
test.
The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins
and associated control signals.
Each SAM3 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit con-
tains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
For more information, please refer to BDSL files available for the SAM3U Series.
• Manchester encoded stream. This is the reset value.
• NRZ_based UART byte structure
• Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to
• Write 0x2 into the Selected Pin Protocol Register
• Write 0x100 into the Formatter and Flush Control Register
• Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the
enable the use of trace and debug blocks.
baud rate of the asynchronous output (this can be done automatically by the debugging tool).
– Select the Serial Wire Output – NRZ
Atmel’s web site
SAM3U Series
to set up the
237
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