ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 326

• Manufacturer Part Number: ATSAM3U4EA-CU
• Description: IC MCU 32BIT 256KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.2.4
22.2.4.1
Table 22-4.
22.2.4.2
326
Step
1
2
3
4
5
6
SAM3U Series
Programmer Handshaking
Programmer Action
Sets MODE and DATA signals
Clears NCMD signal
Waits for RDY low
Releases MODE and DATA signals
Sets NCMD signal
Waits for RDY high
Write Handshaking
Read Handshaking
Write Handshake
A handshake is defined for read and write operations. When the device is ready to start a new
operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal.
The handshaking is achieved once NCMD signal is high and RDY is high.
For details on the write handshaking sequence, refer to
Figure 22-2. Parallel Programming Timing, Write Sequence
For details on the read handshaking sequence, refer to
• Apply XIN clock
• Wait for 20 ms
• Start a read or write handshaking.
MODE[3:0]
DATA[15:0]
NVALID
NCMD
NOE
RDY
1
Waits for NCMD low
Latches MODE and DATA
Clears RDY signal
Executes command and polls NCMD high
Executes command and polls NCMD high
Sets RDY
Device Action
2
3
Figure 22-3
Figure 22-2
4
5
and
and
Data I/O
Input
Input
Input
Input
Input
Input
Table
Table
6430D–ATARM–25-Mar-11
22-5.
22-4.