ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 254
![IC MCU 32BIT 256KB FLSH 144LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
ATSAM3U4EA-CU
Manufacturer Part Number
ATSAM3U4EA-CU
Description
IC MCU 32BIT 256KB FLSH 144LFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4EA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 16-7.
254
if (URSTEN = 0) and
SAM3U Series
Peripheral Access
(URSTIEN = 1)
Reset Controller Status and Interrupt
URSTS
NRSTL
rstc_irq
NRST
MCK
resynchronization
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
further software reset should be performed until the end of the current one. This bit is
automatically cleared at the end of the current software reset.
each MCK rising edge.
register. This transition is also detected on the Master Clock (MCK) rising edge (see
16-7). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the
URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the
RSTC_SR status register resets the URSTS bit and clears the interrupt.
2 cycle
resynchronization
2 cycle
RSTC_SR
read
6430D–ATARM–25-Mar-11
Figure
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