P80C32X2BBD,157 NXP Semiconductors, P80C32X2BBD,157 Datasheet - Page 50

• Manufacturer Part Number: P80C32X2BBD,157
• Description: IC 80C51 MCU 256 ROMLESS 44LQFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C32X2BBD,157

• Program Memory Type: ROMless
• Package / Case: 44-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P80C3x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935272087157; P80C32X2BBD; P80C32X2BBD

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V
3. V
4. Bit is output on P0.4 (1 = 12x, 0 = 6x).
5. Security bit one is output on P0.7.
*
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
Philips Semiconductors
Table 9. EPROM Programming Modes
NOTES:
Table 10. Program Security Bits for EPROM Devices
NOTES:
2003 Jan 24
Read signature
Program code data
Verify code data
Pgm encryption table
Pgm security bit 1
Pgm security bit 2
Pgm security bit 3
Program to 6-clock mode
Verify 6-clock
Verify security bits
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Security bit two is output on P0.6.
Security bit three is output on P0.3.
ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while V
12.75 V. Each programming pulse is low for 100 s ( 10 s) and high for a minimum of 10 s.
1
2
3
4
PP
CC
PROGRAM LOCK BITS
= 12.75 V 0.25 V.
= 5 V 10% during programming and verification.
SB1
MODE
U
P
P
P
4
5
SB2
U
U
P
P
1, 2
SB3
U
U
U
P
RST
1
1
1
1
1
1
1
1
1
1
PROTECTION DESCRIPTION
No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if
programmed.)
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM
is disabled.
Same as 2, also verify is disabled.
Same as 3, external execution is disabled. Internal data RAM is not accessible.
PSEN
0
0
0
0
0
0
0
0
0
0
ALE/PROG
0*
0*
0*
0*
0*
0*
1
1
1
1
50
EA/V
V
V
V
V
V
V
1
1
1
1
PP
PP
PP
PP
PP
PP
PP
P2.7
0
1
0
1
1
1
0
0
e
e
P2.6
0
0
0
0
1
1
1
0
0
0
P80C3xX2; P80C5xX2;
P3.7
0
1
1
1
1
0
0
1
0
1
P3.6
P87C5xX2
0
1
1
0
1
0
1
0
1
0
PP
Product data
is held at
P3.3
X
X
X
X
X
X
X
X
0
1