P80C32X2FN,112 NXP Semiconductors, P80C32X2FN,112 Datasheet - Page 45

• Manufacturer Part Number: P80C32X2FN,112
• Description: IC 80C51 MCU 256 ROMLESS 40DIP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C32X2FN,112

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Processor Series: P80C3x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935269611112; P80C32X2FN; P80C32X2FN

Philips Semiconductors
2003 Jan 24
WRITE TO SBUF
INSTRUCTION
PORT 0
PORT 2
INPUT DATA
OUTPUT DATA
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
CLEAR RI
PSEN
ALE
WR
CLOCK
ALE
t
AVLL
0
t
QVXH
FROM RI OR DPL
A0–A7
t
t
1
XHDV
LLAX
t
AVWL
0
t
t
XLXL
VALID
LLWL
V
CC
0.45V
–0.5
P2.0–P2.7 OR A8–A15 FROM DPF
Figure 29. External Data Memory Write Cycle
t
XHQX
2
Figure 30. Shift Register Mode Timing
VALID
1
t
QVWX
Figure 31. External Clock Drive
0.2V
t
CHCL
0.7V
t
CC
t
XHDX
DATA OUT
QVWH
CC
3
t
WLWH
–0.1
VALID
2
45
t
CLCX
4
t
CLCL
VALID
3
t
CHCX
t
CLCH
t
WHLH
t
5
WHQX
VALID
SU00009
4
A0–A7 FROM PCL
A0–A15 FROM PCH
P80C3xX2; P80C5xX2;
6
VALID
5
7
VALID
6
P87C5xX2
INSTR IN
Product data
8
VALID
SU00026
SET TI
SET RI
SU00027
7