P87C52UBPN,112 NXP Semiconductors, P87C52UBPN,112 Datasheet - Page 33
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P87C52UBPN,112
Manufacturer Part Number
P87C52UBPN,112
Description
IC 80C51 MCU 256 RAM 40DIP
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet
1.P87C52UBAA512.pdf
(38 pages)
Specifications of P87C52UBPN,112
Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Package
40PDIP
Device Core
80C51
Family Name
87C
Maximum Speed
33 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
UART
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
935253730112
P87C52UBPN
P87C52UBPN
P87C52UBPN
P87C52UBPN
*
**
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
Philips Semiconductors
NOTES:
MASK ROM DEVICES
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 10) is programmed, MOVC instructions executed from
external program memory are disabled from fetching code bytes
Table 10. Program Security Bits
NOTES:
2000 Aug 07
PROGRAM LOCK BITS
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
FOR PROGRAMMING CONFIGURATION SEE FIGURE 26.
FOR VERIFICATION CONDITIONS SEE FIGURE 28.
SEE TABLE 8.
1
2
P0.0 – P0.7
ALE/PROG
(A0 – A12)
P1.0–P1.7
P2.0–P2.5
(D0 – D7)
PORT 0
EA/V
P2.7
P3.4
PP
**
SB1
U
P
SB2
U
U
1, 2
t
t
AVGL
DVGL
t
EHSH
PROTECTION DESCRIPTION
No Program Security features enabled.
(Code verify will still be encrypted by the Encryption Array if programmed.)
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.
t
SHGL
t
GLGH
PROGRAMMING
Figure 29. EPROM Programming and Verification
ADDRESS
DATA IN
*
t
GHGL
LOGIC 0
t
t
GHDX
GHAX
33
t
GHSL
from the internal memory, EA is latched on Reset and all further
programming of the EPROM is disabled. When security bits 1 and 2
are programmed, in addition to the above, verify mode is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
LOGIC 1
t
ELQV
80C51/87C51/80C52/87C52
VERIFICATION
t
AVQV
ADDRESS
LOGIC 1
DATA OUT
*
t
EHQZ
Product specification
SU01414