P89LPC932A1FA,112 NXP Semiconductors, P89LPC932A1FA,112 Datasheet - Page 54

• Manufacturer Part Number: P89LPC932A1FA,112
• Description: IC 80C51 MCU FLASH 8K 28-PLCC
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC932A1FA,112

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-PLCC
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• For Use With: OM6292 - DEMO BOARD PCA2125 RTCDB-TSSOP-LPC932 - BOARD FOR LPC932 TSSOP622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1003 - KIT FOR LCD DEMO622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4279-5; 935276131112; P89LPC932A1FA

NXP Semiconductors
Table 11.
V
T
P89LPC932A1_3
Product data sheet
Symbol
t
t
t
VR
RH
RL
amb
Fig 27. SPI slave timing (CPHA = 1)
DD
Fig 28. ISP entry waveform
= 2.4 V to 3.6 V, unless otherwise specified.
= 40 C to +85 C for industrial applications, unless otherwise specified.
Dynamic characteristics, ISP entry mode
Parameter
V
RST HIGH time
RST LOW time
(CPOL = 0)
(CPOL = 1)
DD
10.2 ISP entry mode
SPICLK
SPICLK
(output)
active to RST active delay time
(input)
(input)
(input)
MISO
MOSI
t
SPIA
SS
V
RST
DD
t
SPILEAD
t
t
SPIOH
SPIR
t
not defined
t
SPIF
SPIDV
t
t
SPICLKH
SPICLKL
t
SPIF
t
SPIDSU
t
VR
slave MSB/LSB out
MSB/LSB in
T
SPICYC
t
RL
Conditions
Rev. 03 — 12 March 2007
t
SPIOH
t
t
t
SPICLKH
t
SPICLKL
SPIDV
SPIDH
8-bit microcontroller with accelerated two-clock 80C51 core
t
t
RH
SPIR
t
SPIR
t
t
SPIDSU
SPIOH
t
SPIDV
Min
50
1
1
t
SPIDSU
slave LSB/MSB out
LSB/MSB in
002aaa912
P89LPC932A1
Typ
-
-
-
t
t
SPIDH
SPILAG
002aaa911
t
SPIR
Max
-
32
-
© NXP B.V. 2007. All rights reserved.
t
SPIDIS
Unit
54 of 64
s
s
s