ADUC812BSZ Analog Devices Inc, ADUC812BSZ Datasheet - Page 24

• Manufacturer Part Number: ADUC812BSZ
• Description: IC ADC 12BIT MULTICH MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC812BSZ

• Core Size: 8-Bit
• Program Memory Size: 8KB (8K x 8)
• Core Processor: 8052
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Eeprom Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 1.3MIPS
• No. Of Timers: 3
• Package: 52MQFP
• Device Core: 8052
• Family Name: ADuC8xx
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: I2C/SPI/TWI/UART
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC812
WDCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Example
To set up the watchdog timer for a timeout period of 2048 ms,
the following code would be used:
MOV
SETB
To prevent the watchdog timer from timing out, the timer
refresh bits need to be set before 2.048 seconds has elapsed.
SETB
SETB
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
within a reasonable amount of time if the ADuC812 enters an
erroneous state, possibly due to a programming error. The Watch-
dog function can be disabled by clearing the WDE (Watchdog
Enable) bit in the Watchdog Control (WDCON) SFR. When
enabled, the watchdog circuit will generate a system reset if the
P
R
E
WDCON,#0E0h
WDE
WDR1
WDR2
2
Name
PRE2
PRE1
PRE0
—
WDR1
WDR2
WDS
WDE
P
R
E
;refresh watchdog timer..
; ..bits must be set in this
;order
1
;2.048 second
;timeout period
;enable watchdog timer
Watchdog Timer
Control Register
C0H
00H
Yes
P
Description
Watchdog Timer Prescale Bits.
PRE2
0
0
0
0
1
1
1
1
Not Used.
Watchdog Timer Refresh Bits. Set sequentially to refresh the watchdog timer.
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters.
R
E
0
Table IX. WDCON SFR Bit Designations
PRE1
0
0
1
1
0
0
1
1
—
PRE0
0
1
0
1
0
1
0
1
–24–
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors both supplies (AV
will indicate when either power supply drops below one of five
user selectable voltage trip points from 2.63 V to 4.63 V. For
correct operation of the Power Supply Monitor function, AV
must be equal to or greater than 2.7 V. The Power Supply
Monitor function is controlled via the PSMCON SFR. If
enabled via the IE2 SFR, the Power Supply Monitor will interrupt
the core using the PSMI bit in the PSMCON SFR. This bit will
not be cleared until the failing power supply has returned
above the trip point for at least 256 ms. This ensures that the
power supply has fully settled before the bit is cleared. This
monitor function allows the user to save working registers to avoid
possible data loss due to the low supply condition, and also ensures
that normal code execution will not resume until a safe supply
level has been well established. The supply monitor is also
protected against spurious glitches triggering the interrupt circuit.
user program fails to set the watchdog timer refresh bits (WDR1,
WDR2) within a predetermined amount of time (see PRE2–0
bits in WDCON). The watchdog timer itself is a 16-bit counter.
The watchdog timeout interval can be adjusted via the PRE2–0 bits
in WDCON. Full Control and Status of the watchdog timer function
can be controlled via the watchdog timer control SFR (WDCON).
W
D
R
1
Timeout Period (ms)
16
32
64
128
256
512
1024
2048
W
D
R
2
DD
and DV
W
D
S
DD
) on the ADuC812. It
W
D
E
REV. E
DD