ADUC812BSZ Analog Devices Inc, ADUC812BSZ Datasheet - Page 48

IC ADC 12BIT MULTICH MCU 52-MQFP

ADUC812BSZ

Manufacturer Part Number
ADUC812BSZ
Description
IC ADC 12BIT MULTICH MCU 52-MQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC812BSZ

Core Size
8-Bit
Program Memory Size
8KB (8K x 8)
Core Processor
8052
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP
Controller Family/series
(8051) 8052
No. Of I/o's
32
Eeprom Memory Size
8KB
Ram Memory Size
256Byte
Cpu Speed
1.3MIPS
No. Of Timers
3
Package
52MQFP
Device Core
8052
Family Name
ADuC8xx
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
I2C/SPI/TWI/UART
On-chip Adc
8-chx12-bit
On-chip Dac
2-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADuC812
Parameter
EXTERNAL DATA MEMORY READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
RLRH
AVLL
LLAX
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
RLAZ
WHLH
RD Pulsewidth
Address Valid after ALE Low
Address Hold after ALE Low
RD Low to Valid Data In
Data and Address Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address Valid to RD or WR Low
RD Low to Address Float
RD or WR High to ALE High
PORT 0 (I/O)
PORT 2 (O)
PSEN (O)
ALE (O)
RD (O)
MCLK
t
AVLL
Figure 52. External Data Memory Read Cycle
A0–A7 (OUT)
A16–A23
t
AVDV
t
LLAX
t
AVWL
t
LLWL
t
LLDV
Min
400
43
48
0
200
203
43
–48–
t
12 MHz
RLAZ
t
RLDV
Max
252
97
300
0
123
517
585
A8–A15
t
DATA (IN)
RLRH
t
RHDX
Min
6t
t
t
0
3t
4t
t
CK
CK
CK
CK
CK
CK
– 40
– 35
– 40
Variable Clock
– 100
– 50
– 130
t
WHLH
t
RHDZ
Max
5t
2t
8t
9t
3t
0
6t
CK
CK
CK
CK
CK
CK
– 70
– 150
– 165
+ 50
– 100
– 165
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. E

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