ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet
ST7FLITEU09M6TR
Specifications of ST7FLITEU09M6TR
Available stocks
Related parts for ST7FLITEU09M6TR
ST7FLITEU09M6TR Summary of contents
Page 1
Features ■ Memories – 2K Bytes single voltage Flash program memory with readout protection, in-circuit and in-application programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55 °C – 128 bytes RAM – 128 bytes data ...
Page 2
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
ST7LITEU05 ST7LITEU09 5.7.1 6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Contents 8.3 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
ST7LITEU05 ST7LITEU09 11.1.4 11.1.5 11.1.6 11.1.7 11.2 12-bit autoreload timer (AT ...
Page 6
Contents 13.1.5 13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
ST7LITEU05 ST7LITEU09 15.3.4 15.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
ST7LITEU05 ST7LITEU09 Table 49. Operating characteristics with LVD ...
Page 10
List of figures List of figures Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
ST7LITEU05 ST7LITEU09 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 12
Introduction 1 Introduction The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7ULTRALITE features Flash memory with byte-by-byte in-circuit programming (ICP) and ...
Page 13
ST7LITEU05 ST7LITEU09 2 Pin description Figure 2. 8-pin SO and DIP package pinout PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 / MCO High sink capability 2. eix : associated external interrupt vector Figure 3. ...
Page 14
Pin description Figure 4. 16-pin package pinout PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 / MCO 1. For development or tool prototyping purposes only. Package not orderable in production quantities. 2. Must be tied to ground Note: ...
Page 15
ST7LITEU05 ST7LITEU09 Legend / Abbreviations for Type input output supply In/Output level: C Output level High sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = weak ...
Page 16
Register & memory map 3 Register & memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory. The RAM space includes ...
Page 17
ST7LITEU05 ST7LITEU09 Table 3. Hardware register map Address Block Register label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h to 000Ah 000Bh Lite LTCSR 000Ch timer LTICR 000Dh ATCSR 000Eh CNTRH 000Fh CNTRL Auto-reload 0010h ATRH timer 0011h ATRL ...
Page 18
Register & memory map Table 3. Hardware register map (continued) Address Block Register label 0049h AWUPR AWU 004Ah AWUCSR 004Bh DMCR 004Ch DMSR 004Dh DMBK1H (4) DM 004Eh DMBK1L 004Fh DMBK2H 0050h DMBK2L 0051h to 007Fh 1. Legend: x=undefined, R/W=read/write ...
Page 19
ST7LITEU05 ST7LITEU09 4 Flash program memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash ...
Page 20
Flash program memory Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) ...
Page 21
ST7LITEU05 ST7LITEU09 ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ...
Page 22
Flash program memory 4.6 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual 4.7 Register description 4.7.1 Flash control/status register (FCSR) This register ...
Page 23
ST7LITEU05 ST7LITEU09 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ...
Page 24
Data EEPROM On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed. 5.3.2 Write operation ...
Page 25
ST7LITEU05 ST7LITEU09 Figure 9. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit Set by USER application E2PGM bit programming cycle is interrupted (by a reset action), the integrity of the data in memory is not ...
Page 26
Data EEPROM 5.6 Data EEPROM readout protection The readout protection is enabled through an option bit (see option byte section). When this option is selected, the programs and data stored in the EEPROM memory are protected against readout (including a ...
Page 27
ST7LITEU05 ST7LITEU09 Table 4. Data EEPROM register map and reset values Address Register Label (Hex.) EECSR 0030h Reset Value Data EEPROM E2LAT E2PGM 27/139 ...
Page 28
Central processing unit 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ...
Page 29
ST7LITEU05 ST7LITEU09 Figure 11. CPU registers 15 PCH RESET VALUE = RESET VECTOR @ FFFEh-FFFFh RESET VALUE = 1 15 RESET VALUE = STACK HIGHER ADDRESS undefined value 6.3.4 Condition code register (CC) The 8-bit condition code ...
Page 30
Central processing unit Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of ...
Page 31
ST7LITEU05 ST7LITEU09 The least significant byte of the Stack Pointer (called S) can be directly accessed instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the ...
Page 32
Supply, reset and clock management 7 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external ...
Page 33
ST7LITEU05 ST7LITEU09 Note: In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in See “Electrical characteristics” on page 95. for more information on the ...
Page 34
Supply, reset and clock management Figure 13. Clock switching Figure 14. Clock management block diagram CR9 internal RC CK2 CLKIN f OSC 34/139 Set RC/AWU Internal RC Poll AWU_FLAG until set Reset RC/AWU AWU RC Poll RC_FLAG until set CR8 ...
Page 35
ST7LITEU05 ST7LITEU09 7.3 Register description 7.3.1 Main clock control/status register (MCCSR) Reset value: 0000 0000 (00h Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable bit This bit is read/write ...
Page 36
Supply, reset and clock management 7.3.3 System integrity (SI) control/status register (SICSR) Reset Value: 0000 0x00 (0xh CR1 Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as ...
Page 37
ST7LITEU05 ST7LITEU09 7.3.5 Clock controller control/status register (CKCNTCSR) Reset Value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware. 0: ...
Page 38
Supply, reset and clock management 7.4 Reset sequence manager (RSM) 7.4.1 Introduction The reset sequence manager includes three Reset sources as shown in ● External RESET source pulse ● Internal LVD Reset (low voltage detection) ● Internal WATCHDOG Reset Note: ...
Page 39
ST7LITEU05 ST7LITEU09 Figure 16. Reset block diagram RESET 1. See “Illegal opcode reset” on page 92. for more details on illegal opcode reset conditions. 7.4.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output ...
Page 40
Supply, reset and clock management 7.4.5 Internal watchdog reset The Reset sequence generated by a internal Watchdog counter overflow is shown in Figure 17. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is ...
Page 41
ST7LITEU05 ST7LITEU09 7.5 Register description 7.5.1 Multiplexed IO reset control register 1 (MUXCR1) Reset value: 0000 0000 (00h) 7 MIR15 MIR14 7.5.2 Multiplexed IO reset control register 0 (MUXCR0) Reset value: 0000 0000 (00h) 7 MIR7 MIR6 Bits 15:0 = ...
Page 42
Interrupts 8 Interrupts The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The maskable ...
Page 43
ST7LITEU05 ST7LITEU09 8.2 External interrupts External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. ...
Page 44
Interrupts Table 10. Interrupt mapping Source N° block RESET TRAP 0 AWU 1 ei0 2 ei1 2) (2) 3 ei2 4 5 ei3 3) (3) 6 ei4 TIMER 9 10 LITE TIMER ...
Page 45
ST7LITEU05 ST7LITEU09 8.3.1 External interrupt control register 1 (EICR1) Reset value: 0000 0000 (00h Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity bits These bits define the interrupt sensitivity for ei2 ...
Page 46
Interrupts Note: 1 These 8 bits can be written only when the I bit in the CC register is set. 2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted ...
Page 47
ST7LITEU05 ST7LITEU09 Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application recommended to pull V conditions. Refer to circuit example in The LVD is an optional ...
Page 48
Interrupts Monitoring the V The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register. If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the IT+(AVD) IT-(AVD) In the case ...
Page 49
ST7LITEU05 ST7LITEU09 Table 13. Description of interrupt events Interrupt event AVD event 8.4.4 Register description System integrity (SI) control/status register (SICSR) Reset value: 0000 0x00 (0xh CR1 Bit 7 = Reserved, must be kept cleared. Bits 6:5 = ...
Page 50
Interrupts AVD threshold selection register (AVDTHCR) Reset value: 0000 0011 (03h) 7 CK2 CK1 Bits 7:5 = CK[2:0] internal RC Prescaler Selection Refer to Section 7.2 on page Bits 4:2 = Reserved, must be kept cleared. Bits 1:0 = AVD[1:0] ...
Page 51
ST7LITEU05 ST7LITEU09 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-Wait) ...
Page 52
Power saving modes Figure 23. Slow mode clock transition 9.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals ...
Page 53
ST7LITEU05 ST7LITEU09 9.4 Active-halt and Halt modes Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘Halt’ instruction. The decision to enter either in Active- Halt or Halt ...
Page 54
Power saving modes Figure 26. Active-halt mode flowchart 1. This delay occurs only if the MCU exits Active-Halt mode by means of a Reset. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite ...
Page 55
ST7LITEU05 ST7LITEU09 Figure 27. Halt timing overview Figure 28. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some ...
Page 56
Power saving modes instruction. The main reason for this is that the I/O may be wrongly configured due to external interference unforeseen logical condition. ● For the same reason, reinitialize the level sensitiveness of each external interrupt ...
Page 57
ST7LITEU05 ST7LITEU09 mode. This connects measured using the main oscillator clock as a reference timebase. AWU_RC Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: ● The MCU can ...
Page 58
Power saving modes Figure 31. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some ...
Page 59
ST7LITEU05 ST7LITEU09 Bit 2 = AWUF Auto Wake Up flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: ...
Page 60
Power saving modes AWUPR AWU The AWUPR prescaler register can be programmed to modify the time during which the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, depending on ...
Page 61
ST7LITEU05 ST7LITEU09 10 I/O ports 10.1 Introduction The I/O port offers different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An ...
Page 62
I/O ports External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts ...
Page 63
ST7LITEU05 ST7LITEU09 Table 19. DR value and output pin status Note: When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as ...
Page 64
I/O ports Figure 32. I/O port general block diagram REGISTER ACCESS DR DDR OR OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( Table 20. I/O port mode options Configuration mode Floating with/without interrupt Input Pull-up with/without ...
Page 65
ST7LITEU05 ST7LITEU09 Table 21. I/O port configurations PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. ...
Page 66
I/O ports 10.3 Unused I/O pins Unused I/O pins must be connected to fixed voltage levels. Refer to 109. 10.4 Low power modes Table 22. Effect of low power modes on I/O ports Mode Wait No effect on I/O ports. ...
Page 67
ST7LITEU05 ST7LITEU09 The I/O port register configurations are summarised in the following table: Table 24. Port configuration Port Pin name PA0:2, PA4:5 (1) Port A PA3 1. IS4[1: the only safe configuration to avoid spurious interrupt in ...
Page 68
On-chip peripherals 11 On-chip peripherals 11.1 Lite timer (LT) 11.1.1 Introduction The Lite Timer can be used for general-purpose timing functions based on a free- running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register ...
Page 69
ST7LITEU05 ST7LITEU09 Figure 34. Lite timer block diagram f OSC 13-bit UPCOUNTER LTICR LTIC INPUT CAPTURE REGISTER 11.1.3 Functional description The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing ...
Page 70
On-chip peripherals A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to ...
Page 71
ST7LITEU05 ST7LITEU09 11.1.5 Low power modes Table 26. Description of low power modes Mode Wait Active-Halt Halt 11.1.6 Interrupts Table 27. Interrupt events Event Interrupt event flag Timebase Event TBF IC Event ICF Note: The TBF and ICF interrupt events ...
Page 72
On-chip peripherals 11.1.7 Register description Lite timer control/status register (LTCSR) Reset Value: 0000 0x00 (0xh) 7 ICIE ICF Bit 7 = ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input ...
Page 73
ST7LITEU05 ST7LITEU09 Bit 1 = WDGE Watchdog Enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled Bit 0 = WDGD Watchdog Reset Delay This bit is set by software cleared by hardware ...
Page 74
On-chip peripherals 11.2 12-bit autoreload timer (AT) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions based on a free-running 12-bit upcounter with a PWM output channel. 11.2.2 Main features ● 12-bit upcounter with ...
Page 75
ST7LITEU05 ST7LITEU09 PWM frequency and duty cycle The PWM signal frequency (f value PWM COUNTER Following the above formula register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). ...
Page 76
On-chip peripherals Figure 39. PWM signal example f COUNTER COUNTER DCR0=FFEh Output compare mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must ...
Page 77
ST7LITEU05 ST7LITEU09 11.2.4 Low power modes Table 29. Description of low power modes Mode Slow Wait Active-halt Halt 11.2.5 Interrupts Table 30. Interrupt events (1) Interrupt event Overflow Event CMP Event 1. The interrupt events are connected to separate interrupt ...
Page 78
On-chip peripherals Bit 2 = OVF Overflow flag. This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter from FFFh to ATR value counter overflow occurred ...
Page 79
ST7LITEU05 ST7LITEU09 Auto reload register (ATRH) Reset value: 0000 0000 (00h Auto reload register (ATRL) Reset value: 0000 0000 (00h) 7 ATR7 ATR6 Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = ATR[11:0] Autoreload Register. ...
Page 80
On-chip peripherals PWM0 control/status register (PWM0CSR) Reset Value: 0000 0000 (00h Bit 7:2 = Reserved, must be kept cleared. Bit 1 = OP0 PWM0 output polarity. This bit is read/write by software and cleared by hardware after ...
Page 81
ST7LITEU05 ST7LITEU09 Table 32. Register map and reset values (continued) Address Register label (Hex.) ATRL 11 Reset Value PWMCR 12 Reset Value PWM0CSR 13 Reset Value DCR0H 17 Reset Value DCR0L 18 Reset Value 11.3 10-bit A/D converter (ADC) 11.3.1 ...
Page 82
On-chip peripherals Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Figure 40. ADC block diagram f CPU AIN0 AIN1 AINx Digital A/D conversion result The ...
Page 83
ST7LITEU05 ST7LITEU09 cycles) and the C the optimum analog to digital conversion accuracy. The total conversion time CONV = SAMPLE While the ADC is on, these two phases are continuously repeated. At the end of each ...
Page 84
On-chip peripherals 11.3.4 Low power modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. Table 33. Effect of low power ...
Page 85
ST7LITEU05 ST7LITEU09 Table 34. Channel selection Note: A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the EOC bit and starts a new conversion. ADC data register high (ADCDRH) Reset value: 0000 0000 (00h) 7 ...
Page 86
On-chip peripherals Bits 1:0 = D[1:0] LSB of analog converted value Table 36. ADC register map and reset values Address Register label (Hex.) ADCCSR 0034h Reset value ADCDRH 0035h Reset value ADCDRL 0036h Reset value 86/139 ...
Page 87
ST7LITEU05 ST7LITEU09 12 Instruction set 12.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Table 37. Description of addressing modes Addressing mode The ST7 instruction set is designed to ...
Page 88
Instruction set Table 38. ST7 addressing mode overview (continued) Mode Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative Note the time the instruction is executed, the Program Counter (PC) ...
Page 89
ST7LITEU05 ST7LITEU09 Table 39. Instructions supporting inherent addressing mode (continued) Inherent instruction SLL, SRL, SRA, RLC, RRC SWAP 12.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Table 40. ...
Page 90
Instruction set Indexed mode (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its ...
Page 91
ST7LITEU05 ST7LITEU09 Table 41. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Short instructions only SLL, SRL, SRA, RLC, RRC 12.1.7 Relative modes (direct, indirect) This addressing mode is used to modify the PC register value by ...
Page 92
Instruction set Table 43. ST7 instruction set (continued) Logical operations Bit operation Conditional bit test and branch Arithmetic operations Shift and rotates Unconditional jump or call Conditional branch Interruption management Condition code flag modification Using a prebyte The instructions are ...
Page 93
ST7LITEU05 ST7LITEU09 Table 44. Illegal opcode detection Mnemo Description ADC Add with carry ADD Addition AND Logical and BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit ...
Page 94
Instruction set Table 44. Illegal opcode detection (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No operation OR OR operation ...
Page 95
ST7LITEU05 ST7LITEU09 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
Page 96
Electrical characteristics Figure 42. Pin input voltage 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these ...
Page 97
ST7LITEU05 ST7LITEU09 2. I must never be exceeded. This is implicitly insured if V INJ(PIN) current must be limited externally to the I V < Negative injection disturbs the analog performance of the device. In particular, ...
Page 98
Electrical characteristics 13.3.2 Operating conditions with low voltage detector (LVD -40 to 125 °C, unless otherwise specified A Table 49. Operating characteristics with LVD Symbol Reset release threshold V IT+ (LVD) Reset generation threshold V IT- (LVD) LVD ...
Page 99
ST7LITEU05 ST7LITEU09 Table 51. Voltage drop between AVD flag set and LVD reset generation Parameter AVD med. threshold - AVD low. threshold AVD high. threshold - AVD low threshold AVD high. threshold - AVD med. threshold AVD low threshold - ...
Page 100
Electrical characteristics Internal RC oscillator calibrated at 3.3 V The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte). Table 53. Internal RC oscillator characteristics (3.3 V calibration) Symbol Parameter Internal RC oscillator f ...
Page 101
ST7LITEU05 ST7LITEU09 13.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values ...
Page 102
Electrical characteristics 13.4.2 Internal RC oscillator supply characteristics Table 55: Internal RC oscillator supply characterisctics Symbol Parameter Supply current in Run mode Supply current in Wait mode I DD Supply current in Slow mode Supply current in Slow-Wait (5) mode ...
Page 103
ST7LITEU05 ST7LITEU09 Figure 46. Typical I Figure 47. Typical I Figure 48. Typical MHz in run mode vs. internal clock frequency and V DD Idd RUN mode @amb vs int clock freq 6. ...
Page 104
Electrical characteristics Figure 49. Idd vs temp @V Figure 50. Idd vs temp @V Figure 51. Idd vs temp @V 104/139 5 V & int MHz DD 6.0 5.0 4.0 3.0 2.0 1.0 0.0 Temp [°C] 5 ...
Page 105
ST7LITEU05 ST7LITEU09 13.4.3 On-chip peripherals Table 56. On-chip peripheral characteristics Symbol Parameter I 12-bit auto-reload timer supply current DD(AT) I ADC supply current when converting DD(ADC) 1. Not tested in production, guaranteed by characterization. 2. Data based on a differential ...
Page 106
Electrical characteristics 13.6 Memory characteristics T = -40 °C to 125 °C, unless otherwise specified A Table 59. RAM and hardware registers Symbol V Data retention mode RM 1. Minimum V supply voltage without losing data stored in RAM (in ...
Page 107
ST7LITEU05 ST7LITEU09 13.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is ...
Page 108
Electrical characteristics Table 62. EMS test results Symbol Parameter Voltage limits to be applied on any I/O pin to induce V FESD a functional disturbance Fast transient voltage burst limits to be applied V through 100 FFTB ...
Page 109
... Electrical sensitivities Symbol LU 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 13.8 I/O port pin characteristics 13 ...
Page 110
Electrical characteristics Table 66. General characteristics (continued) Symbol Parameter C I/O pin capacitance IO Output high to low level fall t (1) f(IO)out time Output low to high level rise t r(IO)out (1) time External interrupt pulse time t (5) ...
Page 111
ST7LITEU05 ST7LITEU09 Figure 54. Typical R 13.8.2 Output driving current Subject to general operating conditions for V Table 67. Output driving current characteristics Symbol Parameter Output low level voltage for PA3/RESET standard I/O pin (see ( Output low ...
Page 112
Electrical characteristics 2. The I current sourced must always respect the absolute maximum rating specified in IO and control pins) must not exceed I VDD 3. Not tested in production, based on characterization results. Figure 55. Typical V Figure 56. ...
Page 113
ST7LITEU05 ST7LITEU09 Figure 58. Typical V Figure 59. Typical V Figure 60. Typical 2.4 V (HS pins 1200 -45°C 1000 25°C 90°C 800 130°C 600 400 200 ...
Page 114
Electrical characteristics Figure 61. Typical V Figure 62. Typical V Figure 63. Typical V 114/139 - 2.4 V (HS pins 1800 -45°C 1600 25°C 90°C 1400 130°C 1200 1000 800 600 400 200 0 ...
Page 115
ST7LITEU05 ST7LITEU09 Figure 64. Typical V 100 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Figure 65. Typical V 200 180 160 140 120 100 2.4 2.6 2.8 3 3.2 3.4 ...
Page 116
Electrical characteristics 13.9 Control pin characteristics 13.9.1 Asynchronous RESET pin T = -40 °C to 125 °C, unless otherwise specified A Table 68. Asynchronous RESET pin characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage ...
Page 117
ST7LITEU05 ST7LITEU09 Figure 66. RESET pin protection when LVD is enabled Required EXTERNAL RESET 0. Please refer to Section 12.2.1: Illegal opcode reset on page 92 conditions The reset network protects the device against parasitic resets. The output ...
Page 118
Electrical characteristics Figure 67. RESET pin protection when LVD is disabled USER EXTERNAL RESET CIRCUIT Required 1. Please refer to Section 12.2.1 on page 92 2. The reset network protects the device against parasitic resets. The output of the external ...
Page 119
ST7LITEU05 ST7LITEU09 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum value). Data guaranteed by Design, not tested in production. 4. The stabilization time of the A/D converter is masked by ...
Page 120
Electrical characteristics Table 72. ADC accuracy with V Symbol ( Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error L 1. Data ...
Page 121
ST7LITEU05 ST7LITEU09 14 Package characteristics In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
Page 122
Package characteristics Table 73. 8-lead very thin fine pitch dual flat no-lead package, mechanical data Dim Values in inches are converted from mm and rounded to 4 decimal ...
Page 123
ST7LITEU05 ST7LITEU09 Table 74. 8-pin plastic small outline package - 150-mil width, mechanical data Dim Values in inches are converted from mm and rounded to 4 decimal ...
Page 124
Package characteristics Table 75. 8-pin plastic dual in-line outline package, 300-mil width, mechanical data Symbol Values in inches are converted from mm and rounded to 4 ...
Page 125
ST7LITEU05 ST7LITEU09 Figure 73. 16-pin plastic dual in-line package, 300-mil width, package outline Table 76. 16-pin plastic dual in-line package, 300-mil width, mechanical data Dim ...
Page 126
Package characteristics Table 77. Package characteristics Symbol Package thermal resistance R thJA (junction to ambient) T Maximum junction temperature Jmax P Power dissipation Dmax 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is ...
Page 127
ST7LITEU05 ST7LITEU09 15 Device configuration and ordering information Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (FASTROM). ST7PLITEU05 and ST7PLITEU09 devices are Factory Advanced Service Technique ROM (FASTROM) versions of ...
Page 128
Device configuration and ordering information Bit 1 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Bit 0 = WDG HALT Watchdog ...
Page 129
... FFh. The selected options are communicated to STMicroelectronics using the correctly completed option list appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics sales organization will be pleased to provide detailed information on contractual points. Device configuration and ordering information 0 ...
Page 130
Device configuration and ordering information Figure 74. ST7LITEU0 ordering information scheme Example: Family ST7 microcontroller family Version F= Flash P= FASTROM Sub-family LITEU05 LITEU09 No. of pins Memory size Package DIP ...
Page 131
... Reference FASTROM Code *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
Page 132
... Development tools Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. ...
Page 133
ST7LITEU05 ST7LITEU09 Table 81. Development tool order codes for the ST7LITEU0x family In-circuit debugger, RLink series Supported Starter kit products without demo board ST7FLITEU05 (2) STX-RLINK ST7FLITEU09 1. Available from ST or from Raisonance, www.raisonance.com 2. USB connection to PC ...
Page 134
Device configuration and ordering information 15.4 ST7 application notes Table 82. ST7 application notes Identification Application Examples AN1658 Serial Numbering Implementation AN1720 Managing the Read-out Protection in Flash Microcontrollers AN1755 A High Resolution/precision Thermometer Using ST7 and NE555 AN1756 Choosing ...
Page 135
ST7LITEU05 ST7LITEU09 Table 82. ST7 application notes (continued) Identification AN1276 BLDC Motor Start Routine for the ST72141 Microcontroller AN1321 Using the ST72141 Motor Control MCU in Sensor Mode AN1325 Using the ST7 USB LOW-SPEED Firmware V4.x AN1445 Emulated 16-bit Slave ...
Page 136
Device configuration and ordering information Table 82. ST7 application notes (continued) Identification AN1015 Software Techniques for Improving Microcontroller EMC Performance AN1040 Monitoring the Vbus Signal for USB Self-Powered Devices AN1070 ST7 Checksum Self-Checking Capability AN1181 Electrostatic Discharge Sensitive Measurement AN1324 ...
Page 137
ST7LITEU05 ST7LITEU09 Table 82. ST7 application notes (continued) Identification AN1796 Field Updates for FLASH Based ST7 Applications Using a PC Comm Port AN1900 Hardware Implementation for ST7DALI-EVAL AN1904 ST7MC Three-phase AC Induction Motor Control Software Library AN1905 ST7MC Three-phase BLDC ...
Page 138
Revision history 16 Revision history Table 83. Document revision history Date Revision 19-Jan-07 0.1 Initial release Added note 1 to Modified “A/D conversion” on page 83 and added “Changing the conversion channel” on page 83 Updated page Modified EOC bit ...
Page 139
... ST7LITEU05 ST7LITEU09 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...