ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet - Page 54

• Manufacturer Part Number: ST7FLITEU09M6TR
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No

Power saving modes
9.4.2
54/139
Figure 26. Active-halt mode flowchart
1. This delay occurs only if the MCU exits Active-Halt mode by means of a Reset.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active-halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘Halt’ instruction when active halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see
Interrupt mapping on page
an interrupt, the main oscillator is immediately turned on and the 256 or 512 CPU cycle
delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which woke it up (see
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a watchdog Reset (see
details).
during the interrupt routine and cleared when the CC register is popped.
HALT INSTRUCTION
(Active Halt enabled)
N
44) or a Reset. When exiting Halt mode by means of a Reset or
INTERRUPT
Y
3)
256 OR 512 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BITS
N
CYCLE
RESET
Y
DELAY
2)
2)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
Section 15.1 on page 127
4)
4)
ST7LITEU05 ST7LITEU09
Figure
28).
Table 10:
for more