STM8L101F3U6TR STMicroelectronics, STM8L101F3U6TR Datasheet - Page 23

• Manufacturer Part Number: STM8L101F3U6TR
• Description: MCU 8BIT 8K FLASH 20UFQFPN
• Manufacturer: STMicroelectronics
• Series: STM8L EnergyLiter

Specifications of STM8L101F3U6TR

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Infrared, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-UFQFPN
• Processor Series: STM8L10x
• Core: STM8
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8L101xx
5
Memory and register map
Figure 8.
1.
2. Refer to
Table 5
address.
registers, and to
lists the boundary addresses for each memory size. The top of the stack is at the RAM end
Table 7
Memory map
for an overview of hardware register mapping, to
Table 8
0x00 7EFF
0x00 7FFF
0x00 9FFF
0x00 05FF
0x00 47FF
0x00 48FF
0x00 49FF
0x00 57FF
0x00 0000
0x00 0600
0x00 4800
0x 004900
0x 004924
0x 004925
0x 004930
0x 004931
0x00 5000
0x00 5800
0x00 7F00
0x00 8000
0x00 807F
0x00 8080
for information on CPU/SWIM/debug module controller registers.
Doc ID 15275 Rev 11
GPIO and peripheral registers
Flash program memory
CPU/SWIM/Debug/ITC
(up to 513 bytes)
(up to 8 Kbytes)
Interrupt vectors
(up to 2 Kbytes)
(1.5 Kbytes)
Data EEPROM
Option bytes
Low-density
Unique ID
Reserved
Reserved
Reserved
including
Reserved
Registers
including
RAM
Stack
(1)
(1)
(1)
(2)
Table 6
for details on I/O port hardware
Memory and register map
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