ST7FLIT19BY0M6 STMicroelectronics, ST7FLIT19BY0M6 Datasheet - Page 21
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ST7FLIT19BY0M6
Manufacturer Part Number
ST7FLIT19BY0M6
Description
IC MCU 8BIT 2K FLASH 16-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLIT15BY1M6.pdf
(159 pages)
Specifications of ST7FLIT19BY0M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLIT1B-D/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-6232 - BOARD EVAL ST7LITE1B,STP5NK60Z497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
7
1
1
1
H
I
N
Z
C
0
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Bit 2 = N Negative
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
(that is, the most significant bit is a logic 1).
zero.
ST7LITE1xB
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