STM8S207C6T6TR STMicroelectronics, STM8S207C6T6TR Datasheet - Page 50

• Manufacturer Part Number: STM8S207C6T6TR
• Description: MCU 8BIT 32K MEMORY 48LQFP
• Manufacturer: STMicroelectronics
• Series: STM8Sr

Specifications of STM8S207C6T6TR

• Mfg Application Notes: STM8S Getting Started
• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.95 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: STM8S20x
• Core: STM8
• Data Bus Width: 8 bit
• Data Ram Size: 6 KB
• Interface Type: CAN,12C,SPI,UART
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 2
• Operating Supply Voltage: 2.95 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Development Tools By Supplier: STICE-SYS001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-10032 - EVAL KIT MOTOR CONTROL STM8S497-10031 - EVAL KIT TOUCH SENSING STM8S497-10592 - BOARD DAUGHTER FOR STM8S207/8497-10593 - KIT STARTER FOR STM8S207/8 SER497-8506 - BOARD EVAL FOR STM8S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Option bytes
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Table 13.
Option byte no.
OPT3
OPT4
OPT5
OPT6
OPT7
Option byte description (continued)
LSI_EN: Low speed internal clock enable
IWDG_HW: Independent watchdog
WWDG_HW: Window watchdog activation
WWDG_HALT: Window watchdog reset on halt
EXTCLK: External clock selection
CKAWUSEL: Auto wakeup unit/clock
PRSC[1:0] AWU clock prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
Reserved
WAITSTATE Wait state configuration
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
This configures the stabilisation time.
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
1 wait state is required if f
0: No wait state
1: 1 wait state
Doc ID 14733 Rev 11
CPU
Description
> 16 MHz.
STM8S207xx, STM8S208xx