ST7FLITE35F2M6 STMicroelectronics, ST7FLITE35F2M6 Datasheet - Page 105

IC MCU 8BIT 8K FLASH 20SOIC

ST7FLITE35F2M6

Manufacturer Part Number
ST7FLITE35F2M6
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets

Specifications of ST7FLITE35F2M6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
LINSCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5085 - EVAL BOARD UNIV MOTOR CONTROL497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode)
11.5.9 LIN Mode - Functional Description.
The block diagram of the Serial Control Interface,
in LIN slave mode is shown in
It uses six registers:
– 3 control registers: SCICR1, SCICR2 and
– 2 status registers: the SCISR register and the
– A baud rate register: LPR mapped at the SCI-
The bits dedicated to LIN are located in the
SCICR3. Refer to the register descriptions in
tion
11.5.9.1 Entering LIN Mode
To use the LINSCI in LIN mode the following con-
figuration must be set in SCICR3 register:
– Clear the M bit to configure 8-bit word length.
– Set the LINE bit.
Master
To enter master mode the LSLV bit must be reset
In this case, setting the SBK bit will send 13 low
bits.
Then the baud rate can programmed using the
SCIBRR, SCIERPR and SCIETPR registers.
In LIN master mode, the Conventional and / or Ex-
tended Prescaler define the baud rate (as in stand-
ard SCI mode)
SCICR3
LHLR register mapped at the SCIERPR address
BRR address and an associated fraction register
LPFR mapped at the SCIETPR address
11.5.10for the definitions of each bit.
Figure
59.
Sec-
Slave
Set the LSLV bit in the SCICR3 register to enter
LIN slave mode. In this case, setting the SBK bit
will have no effect.
In LIN Slave mode the LIN baud rate generator is
selected instead of the Conventional or Extended
Prescaler. The LIN baud rate generator is com-
mon to the transmitter and the receiver.
Then the baud rate can be programmed using
LPR and LPRF registers.
Note: It is mandatory to set the LIN configuration
first before programming LPR and LPRF, because
the LIN configuration uses a different baud rate
generator from the standard one.
11.5.9.2 LIN Transmission
In LIN mode the same procedure as in SCI mode
has to be applied for a LIN transmission.
To transmit the LIN Header the proceed as fol-
lows:
– First set the SBK bit in the SCICR2 register to
– reset the SBK bit
– Load the LIN Synch Field (0x55) in the SCIDR
– Wait until the SCIDR is empty (TDRE bit set in
– Load the LIN message Identifier in the SCIDR
start transmitting a 13-bit LIN Synch Break
register to request Synch Field transmission
the SCISR register)
register to request Identifier transmission.
ST7LITE3xF2
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