ST72F623F2M1TR STMicroelectronics, ST72F623F2M1TR Datasheet - Page 13
ST72F623F2M1TR
Manufacturer Part Number
ST72F623F2M1TR
Description
IC MCU 8BIT 8K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F622L2M1.pdf
(139 pages)
Specifications of ST72F623F2M1TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 3 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (2Mb)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
Address
002Ch
002Dh
002Ah
002Bh
002Eh
002Fh
003Ah
003Fh
0025h
0026h
0027h
0028h
0029h
0030h
0031h
0032h
0035h
0036h
0037h
0038h
0039h
to
to
FLASH
Block
USB
TBU
USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
TBUCV
TBUCSR
FCSR
ITRFRE2
Register
Label
USB PID Register
USB DMA Address register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
TBU Counter Value Register
TBU Control/Status Register
Flash Control/Status Register
Interrupt Register 2
Reserved Area (4 Bytes)
Reserved Area (6 Bytes)
Doc ID 6996 Rev 5
Register Name
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
Status
Reset
00h
00h
06h
00h
80h
00h
00h
00h
00h
x0h
xxh
x0h
ST7262xxx
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
13/139
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