STM32F101C8T6TR STMicroelectronics, STM32F101C8T6TR Datasheet - Page 64

• Manufacturer Part Number: STM32F101C8T6TR
• Description: MCU ARM 64KB FLASH MEM 48-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101C8T6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: STM32F101x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 10 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• For Use With: 497-10030 - STARTER KIT FOR STM32497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
Figure 30. SPI timing diagram - slave mode and CPHA = 0
Figure 31. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3V
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OUT P UT
OUT P UT
NSS input
NSS input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
I NPUT
I NPUT
MISO
MISO
MOSI
MOSI
t a(SO)
t SU(NSS)
t a(SO)
t su(SI)
t w(SCKH)
t w(SCKL)
t w(SCKH)
t w(SCKL)
t su(SI)
t SU(NSS)
MS B O UT
t v(SO)
M SB IN
M SB IN
t h(SI)
MS B O UT
t c(SCK)
t v(SO)
Doc ID 13586 Rev 14
t h(SI)
DD
t c(SCK)
and 0.7V
BI T6 OUT
B I T1 IN
t h(SO)
DD
.
B I T1 IN
BI T6 OUT
(1)
t h(SO)
STM32F101x8, STM32F101xB
LSB IN
t r(SCK)
t f(SCK)
LSB OUT
t r(SCK)
t f(SCK)
t h(NSS)
LSB IN
t h(NSS)
LSB OUT
t dis(SO)
t dis(SO)
ai14134c
ai14135