ST72F321J7T6 STMicroelectronics, ST72F321J7T6 Datasheet - Page 30
![MCU 8BIT 48KB FLASH 44TQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72F321J7T6
Manufacturer Part Number
ST72F321J7T6
Description
MCU 8BIT 48KB FLASH 44TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F321AR7T6.pdf
(193 pages)
Specifications of ST72F321J7T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20-DVP3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-4843
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ST72321Rx ST72321ARx ST72321Jx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
Figure 17. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generate an interrupt if
the corresponding Enable Control Bit (AVDIE) is
30/193
WAIT
HALT
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
Mode
V
V
IT+(EVD)
IT-(EVD)
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
The SICSR register is frozen.
V
EVD
0
Description
INTERRUPT PROCESS
V
hyst
1
of the comparator output. This means it is generat-
ed when either one of these two events occur:
The EVD function is illustrated in
For more details, refer to the Electrical Character-
istics section.
set and the interrupt mask in the CC register is re-
set (RIM instruction).
AVD event
– V
– V
Interrupt Event
EVD
EVD
rises up to V
falls down to V
Event
AVDF
Flag
IT+(EVD)
IT-(EVD)
Control
Enable
AVDIE
Bit
INTERRUPT PROCESS
Figure
0
from
Wait
Exit
Yes
17.
from
Exit
Halt
No