ST72F321J7T6 STMicroelectronics, ST72F321J7T6 Datasheet - Page 92
![MCU 8BIT 48KB FLASH 44TQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72F321J7T6
Manufacturer Part Number
ST72F321J7T6
Description
MCU 8BIT 48KB FLASH 44TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F321AR7T6.pdf
(193 pages)
Specifications of ST72F321J7T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20-DVP3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-4843
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ST72321Rx ST72321ARx ST72321Jx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 57. Data Clock Timing Diagram
92/193
(from slave)
(from slave)
57).
(to slave)
(to slave)
(from master)
(from master)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
SS
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit
MSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
CPHA =0
CPHA =1
Bit 4
Bit 4
Bit 4
Bit 4
Figure
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit3
Bit3
Bit3
Bit3
57, shows an SPI transfer with the four
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
LSBit
LSBit
LSBit
LSBit